dts/marvell/cn9130-cf-pro.dts

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 	compatible = "solidrun,cn9130-clearfog-pro",
21 		     "solidrun,cn9130-sr-som", "marvell,cn9130";
23 	gpio-keys {
24 		compatible = "gpio-keys";
25 		pinctrl-0 = <&rear_button_pins>;
26 		pinctrl-names = "default";
28 		button-0 {
32 			linux,can-disable;
38 /* SRDS #3 - SGMII 1GE to L2 switch */
41 	phy-mode = "sgmii";
44 	fixed-link {
45 		speed = <1000>;
46 		full-duplex;
53 	 * - LED[0]: link/activity: On/blink (green)
54 	 * - LED[1]: link is 100/1000Mbps: On (red)
55 	 * - LED[2]: high impedance (floating)
58 	 * - LED0: link/activity: On/blink (green)
59 	 * - LED1: link is 1000Mbps: On (red)
63 	marvell,reg-init = <3 16 0xf000 0x0a61>;
66 		#address-cells = <1>;
67 		#size-cells = <0>;
69 		led@0 {
74 			default-state = "keep";
77 		led@1 {
82 			default-state = "keep";
88 	ethernet-switch@4 {
91 		pinctrl-0 = <&dsa_clk_pins &dsa_pins>;
92 		pinctrl-names = "default";
93 		reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
94 		interrupt-parent = <&cp0_gpio1>;
97 		ethernet-ports {
98 			#address-cells = <1>;
99 			#size-cells = <0>;
101 			ethernet-port@0 {
107 					#address-cells = <1>;
108 					#size-cells = <0>;
110 					led@0 {
115 						default-state = "keep";
118 					led@1 {
123 						default-state = "keep";
128 			ethernet-port@1 {
134 					#address-cells = <1>;
135 					#size-cells = <0>;
137 					led@0 {
142 						default-state = "keep";
145 					led@1 {
150 						default-state = "keep";
155 			ethernet-port@2 {
161 					#address-cells = <1>;
162 					#size-cells = <0>;
164 					led@0 {
169 						default-state = "keep";
172 					led@1 {
177 						default-state = "keep";
182 			ethernet-port@3 {
188 					#address-cells = <1>;
189 					#size-cells = <0>;
191 					led@0 {
196 						default-state = "keep";
199 					led@1 {
204 						default-state = "keep";
209 			ethernet-port@4 {
215 					#address-cells = <1>;
216 					#size-cells = <0>;
218 					led@0 {
223 						default-state = "keep";
226 					led@1 {
231 						default-state = "keep";
236 			ethernet-port@5 {
240 				phy-mode = "sgmii";
242 				fixed-link {
243 					speed = <1000>;
244 					full-duplex;
248 			ethernet-port@6 {
251 				phy-mode = "rgmii";
258 				fixed-link {
259 					speed = <1000>;
260 					full-duplex;
266 			#address-cells = <1>;
267 			#size-cells = <0>;
269 			switch0phy0: ethernet-phy@0 {
273 			switch0phy1: ethernet-phy@1 {
281 				marvell,reg-init = <3 16 0xf000 0x0a61>;
284 			switch0phy2: ethernet-phy@2 {
288 			switch0phy3: ethernet-phy@3 {
292 			switch0phy4: ethernet-phy@4 {
302 		 * mdio-external {
303 		 *	compatible = "marvell,mv88e6xxx-mdio-external";
304 		 *	#address-cells = <1>;
305 		 *	#size-cells = <0>;
307 		 *	ethernet-phy@1 {
315 /* SRDS #4 - miniPCIe (CON2) */
317 	num-lanes = <1>;
319 	/* dw-pcie inverts internally */
320 	reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
325 	dsa_clk_pins: cp0-dsa-clk-pins {
330 	dsa_pins: cp0-dsa-pins {
335 	rear_button_pins: cp0-rear-button-pins {
340 	cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
347 	/* add pin for chip-select 1 on mikrobus */
348 	pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
351 /* USB-2.0 Host on Type-A connector */
354 	phy-names = "utmi";
361 	pcie1-0-clkreq-hog {
362 		gpio-hog;
365 		line-name = "pcie1.0-clkreq";
369 	pcie1-0-w-disable-hog {
370 		gpio-hog;
372 		output-low;
373 		line-name = "pcie1.0-w-disable";