Lines Matching +full:armada +full:- +full:ap806 +full:- +full:sdhci
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device Tree file for Marvell Armada AP80x.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
36 * mainline U-Boot, and should be updated by the
40 psci-area@4000000 {
42 no-map;
47 no-map;
52 #address-cells = <2>;
53 #size-cells = <2>;
54 compatible = "simple-bus";
55 interrupt-parent = <&gic>;
58 config-space@f0000000 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "simple-bus";
65 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
67 dma-coherent;
68 #iommu-cells = <1>;
69 #global-interrupts = <1>;
82 gic: interrupt-controller@210000 {
83 compatible = "arm,gic-400";
84 #interrupt-cells = <3>;
85 #address-cells = <1>;
86 #size-cells = <1>;
88 interrupt-controller;
96 compatible = "arm,gic-v2m-frame";
97 msi-controller;
99 arm,msi-base-spi = <160>;
100 arm,msi-num-spis = <32>;
103 compatible = "arm,gic-v2m-frame";
104 msi-controller;
106 arm,msi-base-spi = <192>;
107 arm,msi-num-spis = <32>;
110 compatible = "arm,gic-v2m-frame";
111 msi-controller;
113 arm,msi-base-spi = <224>;
114 arm,msi-num-spis = <32>;
117 compatible = "arm,gic-v2m-frame";
118 msi-controller;
120 arm,msi-base-spi = <256>;
121 arm,msi-num-spis = <32>;
126 compatible = "arm,armv8-timer";
134 compatible = "arm,cortex-a72-pmu";
135 interrupt-parent = <&pic>;
140 compatible = "marvell,odmi-controller";
141 msi-controller;
142 marvell,odmi-frames = <4>;
147 marvell,spi-base = <128>, <136>, <144>, <152>;
151 compatible = "marvell,ap806-gicp";
153 marvell,spi-ranges = <64 64>, <288 64>;
154 msi-controller;
157 pic: interrupt-controller@3f0100 {
158 compatible = "marvell,armada-8k-pic";
160 #interrupt-cells = <1>;
161 interrupt-controller;
165 sei: interrupt-controller@3f0200 {
166 compatible = "marvell,ap806-sei";
169 #interrupt-cells = <1>;
170 interrupt-controller;
171 msi-controller;
175 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
178 msi-parent = <&gic_v2m0>;
180 dma-coherent;
184 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
187 msi-parent = <&gic_v2m0>;
189 dma-coherent;
193 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
196 msi-parent = <&gic_v2m0>;
198 dma-coherent;
202 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
205 msi-parent = <&gic_v2m0>;
207 dma-coherent;
211 compatible = "marvell,armada-380-spi";
213 #address-cells = <1>;
214 #size-cells = <0>;
221 compatible = "marvell,mv78230-i2c";
223 #address-cells = <1>;
224 #size-cells = <0>;
231 compatible = "snps,dw-apb-uart";
233 reg-shift = <2>;
235 reg-io-width = <1>;
241 compatible = "snps,dw-apb-uart";
243 reg-shift = <2>;
245 reg-io-width = <1>;
252 compatible = "arm,sbsa-gwdt";
258 compatible = "marvell,armada-ap806-sdhci";
261 clock-names = "core";
263 dma-coherent;
264 marvell,xenon-phy-slow-mode;
268 ap_syscon0: system-controller@6f4000 {
269 compatible = "syscon", "simple-mfd";
273 compatible = "marvell,ap806-pinctrl";
275 uart0_pins: uart0-pins {
282 compatible = "marvell,armada-8k-gpio";
285 gpio-controller;
286 #gpio-cells = <2>;
287 gpio-ranges = <&ap_pinctrl 0 0 20>;
288 marvell,pwm-offset = <0x10c0>;
289 #pwm-cells = <2>;
294 ap_syscon1: system-controller@6f8000 {
295 compatible = "syscon", "simple-mfd";
297 #address-cells = <1>;
298 #size-cells = <1>;
300 ap_thermal: thermal-sensor@80 {
301 compatible = "marvell,armada-ap806-thermal";
303 interrupt-parent = <&sei>;
305 #thermal-sensor-cells = <1>;
318 thermal-zones {
319 ap_thermal_ic: ap-ic-thermal {
320 polling-delay-passive = <0>; /* Interrupt driven */
321 polling-delay = <0>; /* Interrupt driven */
323 thermal-sensors = <&ap_thermal 0>;
326 ap_crit: ap-crit {
333 cooling-maps { };
336 ap_thermal_cpu0: ap-cpu0-thermal {
337 polling-delay-passive = <1000>;
338 polling-delay = <1000>;
340 thermal-sensors = <&ap_thermal 1>;
343 cpu0_hot: cpu0-hot {
348 cpu0_emerg: cpu0-emerg {
355 cooling-maps {
356 map0_hot: map0-hot {
358 cooling-device = <&cpu0 1 2>,
361 map0_emerg: map0-ermerg {
363 cooling-device = <&cpu0 3 3>,
369 ap_thermal_cpu1: ap-cpu1-thermal {
370 polling-delay-passive = <1000>;
371 polling-delay = <1000>;
373 thermal-sensors = <&ap_thermal 2>;
376 cpu1_hot: cpu1-hot {
381 cpu1_emerg: cpu1-emerg {
388 cooling-maps {
389 map1_hot: map1-hot {
391 cooling-device = <&cpu0 1 2>,
394 map1_emerg: map1-emerg {
396 cooling-device = <&cpu0 3 3>,
402 ap_thermal_cpu2: ap-cpu2-thermal {
403 polling-delay-passive = <1000>;
404 polling-delay = <1000>;
406 thermal-sensors = <&ap_thermal 3>;
409 cpu2_hot: cpu2-hot {
414 cpu2_emerg: cpu2-emerg {
421 cooling-maps {
422 map2_hot: map2-hot {
424 cooling-device = <&cpu2 1 2>,
427 map2_emerg: map2-emerg {
429 cooling-device = <&cpu2 3 3>,
435 ap_thermal_cpu3: ap-cpu3-thermal {
436 polling-delay-passive = <1000>;
437 polling-delay = <1000>;
439 thermal-sensors = <&ap_thermal 4>;
442 cpu3_hot: cpu3-hot {
447 cpu3_emerg: cpu3-emerg {
454 cooling-maps {
455 map3_hot: map3-bhot {
457 cooling-device = <&cpu2 1 2>,
460 map3_emerg: map3-emerg {
462 cooling-device = <&cpu2 3 3>,