Lines Matching +full:0 +full:xfd4c0000
20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
68 reg = <0x0 0xc0001000 0x1000>,
69 <0x0 0xc0002000 0x2000>,
70 <0x0 0xc0004000 0x2000>,
71 <0x0 0xc0006000 0x2000>;
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
92 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
99 #clock-cells = <0>;
116 reg = <0x0 0xc1b00000 0x1000>;
136 reg = <0x0 0xfd100000 0x1000>;
143 reg = <0x0 0xfd200000 0x1000>;
150 reg = <0x0 0xfe000000 0x1000>;
151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
158 reg = <0x0 0xfe100000 0x1000>;
166 reg = <0x0 0xfe200000 0x1000>;
174 reg = <0x0 0xfe800000 0x1000>;
181 reg = <0x0 0xfe900000 0x1000>;
188 reg = <0x0 0xc1128000 0x1000>;
198 reg = <0x0 0xfd400000 0x1000>;
207 reg = <0x0 0xfd410000 0x1000>;
216 reg = <0x0 0xfd420000 0x1000>;
225 reg = <0x0 0xfd430000 0x1000>;
233 reg = <0x0 0xfd440000 0x1000>;
242 reg = <0x0 0xfd450000 0x1000>;
251 reg = <0x0 0xfd460000 0x1000>;
260 reg = <0x0 0xfd470000 0x1000>;
269 reg = <0x0 0xfd480000 0x1000>;
278 reg = <0x0 0xfd490000 0x1000>;
287 reg = <0x0 0xfd4a0000 0x1000>;
296 reg = <0x0 0xfd4b0000 0x1000>;
304 reg = <0x0 0xfd4c0000 0x1000>;
313 reg = <0x0 0xfd4d0000 0x1000>;
322 reg = <0x0 0xfd4e0000 0x1000>;
331 reg = <0x0 0xfd4f0000 0x1000>;
340 reg = <0x0 0xfd500000 0x1000>;
349 reg = <0x0 0xfd510000 0x1000>;