Lines Matching +full:4 +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
214 cache-level = <2>;
215 cache-unified;
218 cluster1_l2: l2-cache1 {
220 cache-level = <2>;
221 cache-unified;
224 cluster2_l2: l2-cache2 {
226 cache-level = <2>;
227 cache-unified;
230 cluster3_l2: l2-cache3 {
232 cache-level = <2>;
233 cache-unified;
237 gic: interrupt-controller@4d000000 {
238 compatible = "arm,gic-v3";
239 #interrupt-cells = <3>;
240 #address-cells = <2>;
241 #size-cells = <2>;
243 interrupt-controller;
244 #redistributor-regions = <1>;
245 redistributor-stride = <0x0 0x30000>;
253 its_dsa: msi-controller@c6000000 {
254 compatible = "arm,gic-v3-its";
255 msi-controller;
256 #msi-cells = <1>;
261 eth2: ethernet-0 {
262 compatible = "hisilicon,hns-nic-v2";
263 ae-handle = <&dsaf0>;
264 port-idx-in-ae = <0>;
265 local-mac-address = [00 00 00 00 00 00];
267 dma-coherent;
270 eth3: ethernet-1 {
271 compatible = "hisilicon,hns-nic-v2";
272 ae-handle = <&dsaf0>;
273 port-idx-in-ae = <1>;
274 local-mac-address = [00 00 00 00 00 00];
276 dma-coherent;
279 eth0: ethernet-4 {
280 compatible = "hisilicon,hns-nic-v2";
281 ae-handle = <&dsaf0>;
282 port-idx-in-ae = <4>;
283 local-mac-address = [00 00 00 00 00 00];
285 dma-coherent;
288 eth1: ethernet-5 {
289 compatible = "hisilicon,hns-nic-v2";
290 ae-handle = <&dsaf0>;
291 port-idx-in-ae = <5>;
292 local-mac-address = [00 00 00 00 00 00];
294 dma-coherent;
298 compatible = "fixed-clock";
299 clock-frequency = <50000000>;
300 #clock-cells = <0>;
304 compatible = "arm,armv8-timer";
312 compatible = "arm,cortex-a57-pmu";
317 compatible = "hisilicon,mbigen-v2";
321 msi-parent = <&its_dsa 0x40080>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 num-pins = <2>;
328 msi-parent = <&its_dsa 0x40000>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 num-pins = <128>;
335 msi-parent = <&its_dsa 0x40040>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 num-pins = <128>;
342 msi-parent = <&its_dsa 0x40085>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 num-pins = <10>;
350 compatible = "hisilicon,mbigen-v2";
354 msi-parent = <&its_dsa 0x40800>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 num-pins = <409>;
360 mbigen_sas0: intc-sas0 {
361 msi-parent = <&its_dsa 0x40900>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 num-pins = <128>;
380 * when iommu-map entry is used along with the PCIe node.
381 * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
384 compatible = "arm,smmu-v3";
386 #iommu-cells = <1>;
387 dma-coherent;
388 hisilicon,broken-prefetch-cmd;
393 compatible = "simple-bus";
394 #address-cells = <2>;
395 #size-cells = <2>;
399 compatible = "hisilicon,hip06-lpc";
400 #size-cells = <1>;
401 #address-cells = <2>;
405 compatible = "ipmi-bt";
413 clock-frequency = <1843200>;
420 compatible = "generic-ohci";
422 interrupt-parent = <&mbigen_usb>;
423 interrupts = <640 4>;
424 dma-coherent;
429 compatible = "generic-ehci";
431 interrupt-parent = <&mbigen_usb>;
432 interrupts = <641 4>;
433 dma-coherent;
438 compatible = "hisilicon,peri-subctrl","syscon";
443 compatible = "hisilicon,dsa-subctrl", "syscon";
448 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
458 compatible = "hisilicon,hns-mdio";
460 subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
461 #address-cells = <1>;
462 #size-cells = <0>;
464 phy0: ethernet-phy@0 {
465 compatible = "ethernet-phy-ieee802.3-c22";
469 phy1: ethernet-phy@1 {
470 compatible = "ethernet-phy-ieee802.3-c22";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 compatible = "hisilicon,hns-dsaf-v2";
479 mode = "6port-16rss";
482 reg-names = "ppe-base", "dsaf-base";
483 interrupt-parent = <&mbigen_dsaf0>;
484 subctrl-syscon = <&dsa_subctrl>;
485 reset-field-offset = <0>;
570 desc-num = <0x400>;
571 buf-size = <0x1000>;
572 dma-coherent;
576 serdes-syscon = <&serdes_ctrl>;
577 port-rst-offset = <0>;
578 port-mode-offset = <0>;
579 media-type = "fiber";
584 serdes-syscon = <&serdes_ctrl>;
585 port-rst-offset = <1>;
586 port-mode-offset = <1>;
587 media-type = "fiber";
590 port@4 {
591 reg = <4>;
592 phy-handle = <&phy0>;
593 serdes-syscon = <&serdes_ctrl>;
594 port-rst-offset = <4>;
595 port-mode-offset = <2>;
596 media-type = "copper";
601 phy-handle = <&phy1>;
602 serdes-syscon = <&serdes_ctrl>;
603 port-rst-offset = <5>;
604 port-mode-offset = <3>;
605 media-type = "copper";
610 compatible = "hisilicon,hip06-sas-v2";
612 sas-addr = [50 01 88 20 16 00 00 00];
613 hisilicon,sas-syscon = <&dsa_subctrl>;
614 ctrl-reset-reg = <0xa60>;
615 ctrl-reset-sts-reg = <0x5a30>;
616 ctrl-clock-ena-reg = <0x338>;
618 queue-count = <16>;
619 phy-count = <8>;
620 dma-coherent;
621 interrupt-parent = <&mbigen_sas0>;
622 interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
623 <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
624 <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
625 <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
626 <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
627 <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
628 <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
629 <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
630 <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
631 <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
632 <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
633 <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
634 <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
635 <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
636 <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
637 <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
638 <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
639 <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
640 <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
641 <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
652 compatible = "hisilicon,hip06-sas-v2";
654 sas-addr = [50 01 88 20 16 00 00 00];
655 hisilicon,sas-syscon = <&pcie_subctl>;
656 hip06-sas-v2-quirk-amt;
657 ctrl-reset-reg = <0xa18>;
658 ctrl-reset-sts-reg = <0x5a0c>;
659 ctrl-clock-ena-reg = <0x318>;
661 queue-count = <16>;
662 phy-count = <8>;
663 dma-coherent;
664 interrupt-parent = <&mbigen_sas1>;
665 interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
666 <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
667 <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
668 <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
669 <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
670 <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
671 <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
672 <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
673 <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
674 <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
675 <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
676 <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
677 <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
678 <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
679 <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
680 <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
681 <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
682 <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
683 <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
684 <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
695 compatible = "hisilicon,hip06-sas-v2";
697 sas-addr = [50 01 88 20 16 00 00 00];
698 hisilicon,sas-syscon = <&pcie_subctl>;
699 ctrl-reset-reg = <0xae0>;
700 ctrl-reset-sts-reg = <0x5a70>;
701 ctrl-clock-ena-reg = <0x3a8>;
703 queue-count = <16>;
704 phy-count = <9>;
705 dma-coherent;
706 interrupt-parent = <&mbigen_sas2>;
707 interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
708 <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
709 <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
710 <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
711 <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
712 <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
713 <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
714 <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
715 <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
716 <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
717 <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
718 <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
719 <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
720 <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
721 <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
722 <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
723 <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
724 <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
725 <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
726 <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
737 compatible = "hisilicon,hip06-pcie-ecam";
740 bus-range = <0 31>;
741 msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
742 msi-map-mask = <0xffff>;
743 #address-cells = <3>;
744 #size-cells = <2>;
746 dma-coherent;
749 #interrupt-cells = <1>;
750 interrupt-map-mask = <0xf800 0 0 7>;
751 interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
752 0x0 0 0 2 &mbigen_pcie0 650 4
753 0x0 0 0 3 &mbigen_pcie0 650 4
754 0x0 0 0 4 &mbigen_pcie0 650 4>;