dts/hisilicon/hip05.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 	compatible = "hisilicon,hip05-d02";
12 	interrupt-parent = <&gic>;
13 	#address-cells = <2>;
14 	#size-cells = <2>;
17 		compatible = "arm,psci-0.2";
22 		#address-cells = <1>;
23 		#size-cells = <0>;
25 		cpu-map {
28 					cpu = <&cpu0>;
31 					cpu = <&cpu1>;
34 					cpu = <&cpu2>;
37 					cpu = <&cpu3>;
42 					cpu = <&cpu4>;
45 					cpu = <&cpu5>;
48 					cpu = <&cpu6>;
51 					cpu = <&cpu7>;
56 					cpu = <&cpu8>;
59 					cpu = <&cpu9>;
62 					cpu = <&cpu10>;
65 					cpu = <&cpu11>;
70 					cpu = <&cpu12>;
73 					cpu = <&cpu13>;
76 					cpu = <&cpu14>;
79 					cpu = <&cpu15>;
84 		cpu0: cpu@20000 {
85 			device_type = "cpu";
86 			compatible = "arm,cortex-a57";
88 			enable-method = "psci";
89 			next-level-cache = <&cluster0_l2>;
92 		cpu1: cpu@20001 {
93 			device_type = "cpu";
94 			compatible = "arm,cortex-a57";
96 			enable-method = "psci";
97 			next-level-cache = <&cluster0_l2>;
100 		cpu2: cpu@20002 {
101 			device_type = "cpu";
102 			compatible = "arm,cortex-a57";
104 			enable-method = "psci";
105 			next-level-cache = <&cluster0_l2>;
108 		cpu3: cpu@20003 {
109 			device_type = "cpu";
110 			compatible = "arm,cortex-a57";
112 			enable-method = "psci";
113 			next-level-cache = <&cluster0_l2>;
116 		cpu4: cpu@20100 {
117 			device_type = "cpu";
118 			compatible = "arm,cortex-a57";
120 			enable-method = "psci";
121 			next-level-cache = <&cluster1_l2>;
124 		cpu5: cpu@20101 {
125 			device_type = "cpu";
126 			compatible = "arm,cortex-a57";
128 			enable-method = "psci";
129 			next-level-cache = <&cluster1_l2>;
132 		cpu6: cpu@20102 {
133 			device_type = "cpu";
134 			compatible = "arm,cortex-a57";
136 			enable-method = "psci";
137 			next-level-cache = <&cluster1_l2>;
140 		cpu7: cpu@20103 {
141 			device_type = "cpu";
142 			compatible = "arm,cortex-a57";
144 			enable-method = "psci";
145 			next-level-cache = <&cluster1_l2>;
148 		cpu8: cpu@20200 {
149 			device_type = "cpu";
150 			compatible = "arm,cortex-a57";
152 			enable-method = "psci";
153 			next-level-cache = <&cluster2_l2>;
156 		cpu9: cpu@20201 {
157 			device_type = "cpu";
158 			compatible = "arm,cortex-a57";
160 			enable-method = "psci";
161 			next-level-cache = <&cluster2_l2>;
164 		cpu10: cpu@20202 {
165 			device_type = "cpu";
166 			compatible = "arm,cortex-a57";
168 			enable-method = "psci";
169 			next-level-cache = <&cluster2_l2>;
172 		cpu11: cpu@20203 {
173 			device_type = "cpu";
174 			compatible = "arm,cortex-a57";
176 			enable-method = "psci";
177 			next-level-cache = <&cluster2_l2>;
180 		cpu12: cpu@20300 {
181 			device_type = "cpu";
182 			compatible = "arm,cortex-a57";
184 			enable-method = "psci";
185 			next-level-cache = <&cluster3_l2>;
188 		cpu13: cpu@20301 {
189 			device_type = "cpu";
190 			compatible = "arm,cortex-a57";
192 			enable-method = "psci";
193 			next-level-cache = <&cluster3_l2>;
196 		cpu14: cpu@20302 {
197 			device_type = "cpu";
198 			compatible = "arm,cortex-a57";
200 			enable-method = "psci";
201 			next-level-cache = <&cluster3_l2>;
204 		cpu15: cpu@20303 {
205 			device_type = "cpu";
206 			compatible = "arm,cortex-a57";
208 			enable-method = "psci";
209 			next-level-cache = <&cluster3_l2>;
212 		cluster0_l2: l2-cache0 {
214 			cache-level = <2>;
215 			cache-unified;
218 		cluster1_l2: l2-cache1 {
220 			cache-level = <2>;
221 			cache-unified;
224 		cluster2_l2: l2-cache2 {
226 			cache-level = <2>;
227 			cache-unified;
230 		cluster3_l2: l2-cache3 {
232 			cache-level = <2>;
233 			cache-unified;
237 	gic: interrupt-controller@8d000000 {
238 		compatible = "arm,gic-v3";
239                 #interrupt-cells = <3>;
240                 #address-cells = <2>;
241                 #size-cells = <2>;
243                 interrupt-controller;
244                 #redistributor-regions = <1>;
245                 redistributor-stride = <0x0 0x30000>;
253 		its_peri: msi-controller@8c000000 {
254 			compatible = "arm,gic-v3-its";
255 			msi-controller;
256 			#msi-cells = <1>;
260 		its_m3: msi-controller@a3000000 {
261 			compatible = "arm,gic-v3-its";
262 			msi-controller;
263 			#msi-cells = <1>;
267 		its_pcie: msi-controller@b7000000 {
268 			compatible = "arm,gic-v3-its";
269 			msi-controller;
270 			#msi-cells = <1>;
274 		its_dsa: msi-controller@c6000000 {
275 			compatible = "arm,gic-v3-its";
276 			msi-controller;
277 			#msi-cells = <1>;
283 		compatible = "fixed-clock";
284 		#clock-cells = <0>;
285 		clock-frequency = <200000000>;
289 		compatible = "arm,armv8-timer";
297 		compatible = "arm,cortex-a57-pmu";
302 		compatible = "simple-bus";
303 		#address-cells = <2>;
304 		#size-cells = <2>;
308 			compatible = "snps,dw-apb-uart";
312 			clock-names = "baudclk", "apb_pclk";
313 			reg-shift = <2>;
314 			reg-io-width = <4>;
319 			compatible = "snps,dw-apb-uart";
323 			clock-names = "baudclk", "apb_pclk";
324 			reg-shift = <2>;
325 			reg-io-width = <4>;
329 		lbc: local-bus@80380000 {
330 			compatible = "hisilicon,hisi-localbus", "simple-bus";
336 			#address-cells = <1>;
337 			#size-cells = <0>;
338 			compatible = "snps,dw-apb-gpio";
342 			porta: gpio-controller@0 {
343 				compatible = "snps,dw-apb-gpio-port";
344 				gpio-controller;
345 				#gpio-cells = <2>;
348 				interrupt-controller;
349 				#interrupt-cells = <2>;
355 			#address-cells = <1>;
356 			#size-cells = <0>;
357 			compatible = "snps,dw-apb-gpio";
361 			portb: gpio-controller@0 {
362 				compatible = "snps,dw-apb-gpio-port";
363 				gpio-controller;
364 				#gpio-cells = <2>;
367 				interrupt-controller;
368 				#interrupt-cells = <2>;