Lines Matching +full:reset +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <2>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
34 d-cache-size = <0x8000>; /* 32 KiB */
35 d-cache-line-size = <64>;
36 d-cache-sets = <128>;
37 i-cache-size = <0x8000>; /* 32 KiB */
38 i-cache-line-size = <64>;
39 i-cache-sets = <256>;
40 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a53";
47 enable-method = "psci";
48 d-cache-size = <0x8000>; /* 32 KiB */
49 d-cache-line-size = <64>;
50 d-cache-sets = <128>;
51 i-cache-size = <0x8000>; /* 32 KiB */
52 i-cache-line-size = <64>;
53 i-cache-sets = <256>;
54 next-level-cache = <&L2>;
58 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 d-cache-size = <0x8000>; /* 32 KiB */
63 d-cache-line-size = <64>;
64 d-cache-sets = <128>;
65 i-cache-size = <0x8000>; /* 32 KiB */
66 i-cache-line-size = <64>;
67 i-cache-sets = <256>;
68 next-level-cache = <&L2>;
72 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 d-cache-size = <0x8000>; /* 32 KiB */
77 d-cache-line-size = <64>;
78 d-cache-sets = <128>;
79 i-cache-size = <0x8000>; /* 32 KiB */
80 i-cache-line-size = <64>;
81 i-cache-sets = <256>;
82 next-level-cache = <&L2>;
86 L2: l2-cache {
88 cache-unified;
89 cache-size = <0x80000>; /* 512 KiB */
90 cache-line-size = <64>;
91 cache-sets = <512>;
92 cache-level = <2>;
95 gic: interrupt-controller@f1001000 {
96 compatible = "arm,gic-400";
103 #address-cells = <0>;
104 #interrupt-cells = <3>;
105 interrupt-controller;
109 compatible = "arm,armv8-timer";
121 compatible = "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <1>;
126 crg: clock-reset-controller@8a22000 {
127 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
129 #clock-cells = <1>;
130 #reset-cells = <2>;
132 gmacphyrst: reset-controller {
133 compatible = "ti,syscon-reset";
134 #reset-cells = <1>;
135 ti,reset-bits = <
142 sysctrl: system-controller@8000000 {
143 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
145 #clock-cells = <1>;
146 #reset-cells = <2>;
149 perictrl: peripheral-controller@8a20000 {
150 compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
151 "simple-mfd";
153 #address-cells = <1>;
154 #size-cells = <1>;
158 compatible = "hisilicon,hi3798cv200-usb2-phy";
162 #address-cells = <1>;
163 #size-cells = <0>;
167 #phy-cells = <0>;
173 #phy-cells = <0>;
179 compatible = "hisilicon,hi3798cv200-usb2-phy";
183 #address-cells = <1>;
184 #size-cells = <0>;
188 #phy-cells = <0>;
194 compatible = "hisilicon,hi3798cv200-combphy";
196 #phy-cells = <1>;
199 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
200 assigned-clock-rates = <100000000>;
201 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
205 compatible = "hisilicon,hi3798cv200-combphy";
207 #phy-cells = <1>;
210 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
211 assigned-clock-rates = <100000000>;
212 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
217 compatible = "pinconf-single";
219 pinctrl-single,register-width = <32>;
220 pinctrl-single,function-mask = <7>;
221 pinctrl-single,gpio-range = <
222 &range 0 8 2 /* GPIO 0 */
223 &range 8 1 0 /* GPIO 1 */
228 &range 16 5 0 /* GPIO 2 */
230 &range 24 4 1 /* GPIO 3 */
234 &range 30 4 2 /* GPIO 4 */
237 &range 38 3 2 /* GPIO 6 */
239 &range 46 8 1 /* GPIO 7 */
240 &range 54 8 1 /* GPIO 8 */
241 &range 64 7 1 /* GPIO 9 */
243 &range 72 6 1 /* GPIO 10 */
246 &range 80 6 1 /* GPIO 11 */
248 &range 88 8 0 /* GPIO 12 */
251 range: gpio-range {
252 #pinctrl-single,gpio-range-cells = <3>;
261 clock-names = "uartclk", "apb_pclk";
270 clock-names = "uartclk", "apb_pclk";
275 compatible = "hisilicon,hix5hd2-i2c";
277 #address-cells = <1>;
278 #size-cells = <0>;
280 clock-frequency = <400000>;
286 compatible = "hisilicon,hix5hd2-i2c";
288 #address-cells = <1>;
289 #size-cells = <0>;
291 clock-frequency = <400000>;
297 compatible = "hisilicon,hix5hd2-i2c";
299 #address-cells = <1>;
300 #size-cells = <0>;
302 clock-frequency = <400000>;
308 compatible = "hisilicon,hix5hd2-i2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
313 clock-frequency = <400000>;
319 compatible = "hisilicon,hix5hd2-i2c";
321 #address-cells = <1>;
322 #size-cells = <0>;
324 clock-frequency = <400000>;
333 num-cs = <1>;
334 cs-gpios = <&gpio7 1 0>;
336 clock-names = "sspclk", "apb_pclk";
337 #address-cells = <1>;
338 #size-cells = <0>;
343 compatible = "snps,dw-mshc";
348 clock-names = "biu", "ciu";
350 reset-names = "reset";
355 compatible = "hisilicon,hi3798cv200-dw-mshc";
362 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
364 reset-names = "reset";
368 gpio0: gpio@8b20000 {
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 gpio-ranges = <&pmx0 0 0 8>;
378 clock-names = "apb_pclk";
382 gpio1: gpio@8b21000 {
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 gpio-ranges = <
398 clock-names = "apb_pclk";
402 gpio2: gpio@8b22000 {
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
412 clock-names = "apb_pclk";
416 gpio3: gpio@8b23000 {
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 gpio-ranges = <
431 clock-names = "apb_pclk";
435 gpio4: gpio@8b24000 {
439 gpio-controller;
440 #gpio-cells = <2>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
445 clock-names = "apb_pclk";
449 gpio5: gpio@8004000 {
453 gpio-controller;
454 #gpio-cells = <2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
458 clock-names = "apb_pclk";
462 gpio6: gpio@8b26000 {
466 gpio-controller;
467 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
472 clock-names = "apb_pclk";
476 gpio7: gpio@8b27000 {
480 gpio-controller;
481 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 gpio-ranges = <&pmx0 0 46 8>;
486 clock-names = "apb_pclk";
490 gpio8: gpio@8b28000 {
494 gpio-controller;
495 #gpio-cells = <2>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 gpio-ranges = <&pmx0 0 54 8>;
500 clock-names = "apb_pclk";
504 gpio9: gpio@8b29000 {
508 gpio-controller;
509 #gpio-cells = <2>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
512 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
514 clock-names = "apb_pclk";
518 gpio10: gpio@8b2a000 {
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
528 clock-names = "apb_pclk";
532 gpio11: gpio@8b2b000 {
536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
540 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
542 clock-names = "apb_pclk";
546 gpio12: gpio@8b2c000 {
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&pmx0 0 88 8>;
556 clock-names = "apb_pclk";
561 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
567 clock-names = "mac_core", "mac_ifc";
571 reset-names = "mac_core", "mac_ifc", "phy";
576 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
582 clock-names = "mac_core", "mac_ifc";
586 reset-names = "mac_core", "mac_ifc", "phy";
591 compatible = "hisilicon,hix5hd2-ir";
599 compatible = "hisilicon,hi3798cv200-pcie";
603 reg-names = "control", "rc-dbi", "config";
604 #address-cells = <3>;
605 #size-cells = <2>;
607 bus-range = <0x00 0xff>;
608 num-lanes = <1>;
612 interrupt-names = "msi";
613 #interrupt-cells = <1>;
614 interrupt-map-mask = <0 0 0 0>;
615 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
620 clock-names = "aux", "pipe", "sys", "bus";
622 reset-names = "soft", "sys", "bus";
624 phy-names = "phy";
629 compatible = "generic-ohci";
635 clock-names = "bus", "clk12", "clk48";
637 reset-names = "bus";
639 phy-names = "usb";
644 compatible = "generic-ehci";
650 clock-names = "bus", "phy", "utmi";
654 reset-names = "bus", "phy", "utmi";
656 phy-names = "usb";