dts/hisilicon/hi3798cv200.dtsi

34 			d-cache-size = <0x8000>; /* 32 KiB */
37 			i-cache-size = <0x8000>; /* 32 KiB */
43 		cpu@1 {
48 			d-cache-size = <0x8000>; /* 32 KiB */
51 			i-cache-size = <0x8000>; /* 32 KiB */
62 			d-cache-size = <0x8000>; /* 32 KiB */
65 			i-cache-size = <0x8000>; /* 32 KiB */
76 			d-cache-size = <0x8000>; /* 32 KiB */
79 			i-cache-size = <0x8000>; /* 32 KiB */
89 		cache-size = <0x80000>; /* 512 KiB */
122 		#address-cells = <1>;
123 		#size-cells = <1>;
129 			#clock-cells = <1>;
134 				#reset-cells = <1>;
145 			#clock-cells = <1>;
153 			#address-cells = <1>;
154 			#size-cells = <1>;
162 				#address-cells = <1>;
171 				usb2_phy1_port1: phy@1 {
172 					reg = <1>;
183 				#address-cells = <1>;
196 				#phy-cells = <1>;
207 				#phy-cells = <1>;
223 				&range 8  1 0  /* GPIO 1 */
225 				&range 13 1 0
226 				&range 14 1 1
227 				&range 15 1 0
229 				&range 21 3 1
230 				&range 24 4 1  /* GPIO 3 */
232 				&range 86 1 1
233 				&range 87 1 0
236 				&range 37 1 2
239 				&range 46 8 1  /* GPIO 7 */
240 				&range 54 8 1  /* GPIO 8 */
241 				&range 64 7 1  /* GPIO 9 */
242 				&range 71 1 0
243 				&range 72 6 1  /* GPIO 10 */
244 				&range 78 1 0
245 				&range 79 1 1
246 				&range 80 6 1  /* GPIO 11 */
247 				&range 70 2 1
277 			#address-cells = <1>;
288 			#address-cells = <1>;
299 			#address-cells = <1>;
310 			#address-cells = <1>;
321 			#address-cells = <1>;
333 			num-cs = <1>;
334 			cs-gpios = <&gpio7 1 0>;
337 			#address-cells = <1>;
391 				&pmx0 0 8 1
392 				&pmx0 1 9 4
393 				&pmx0 5 13 1
394 				&pmx0 6 14 1
395 				&pmx0 7 15 1
427 				&pmx0 6 86 1
428 				&pmx0 7 87 1
443 			gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
512 			gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
526 			gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
585 				 <&gmacphyrst 1>;
608 			num-lanes = <1>;
613 			#interrupt-cells = <1>;