dts/freescale/s32v234.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
4  * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&gic>;
14 	#address-cells = <2>;
15 	#size-cells = <2>;
23 		#address-cells = <2>;
24 		#size-cells = <0>;
28 			compatible = "arm,cortex-a53";
30 			enable-method = "spin-table";
31 			cpu-release-addr = <0x0 0x80000000>;
32 			next-level-cache = <&cluster0_l2_cache>;
37 			compatible = "arm,cortex-a53";
39 			enable-method = "spin-table";
40 			cpu-release-addr = <0x0 0x80000000>;
41 			next-level-cache = <&cluster0_l2_cache>;
46 			compatible = "arm,cortex-a53";
48 			enable-method = "spin-table";
49 			cpu-release-addr = <0x0 0x80000000>;
50 			next-level-cache = <&cluster1_l2_cache>;
55 			compatible = "arm,cortex-a53";
57 			enable-method = "spin-table";
58 			cpu-release-addr = <0x0 0x80000000>;
59 			next-level-cache = <&cluster1_l2_cache>;
62 		cluster0_l2_cache: l2-cache0 {
64 			cache-level = <2>;
65 			cache-unified;
68 		cluster1_l2_cache: l2-cache1 {
70 			cache-level = <2>;
71 			cache-unified;
76 		compatible = "arm,armv8-timer";
85 		/* clock-frequency might be modified by u-boot, depending on the
88 		clock-frequency = <10000000>;
91 	gic: interrupt-controller@7d001000 {  label
92 		compatible = "arm,cortex-a15-gic";
93 		#interrupt-cells = <3>;
94 		#address-cells = <0>;
95 		interrupt-controller;
105 		#address-cells = <2>;
106 		#size-cells = <2>;
107 		compatible = "simple-bus";
108 		interrupt-parent = <&gic>;
112 			compatible = "simple-bus";
113 			#address-cells = <2>;
114 			#size-cells = <2>;
115 			interrupt-parent = <&gic>;
120 				compatible = "fsl,s32v234-linflexuart";
128 			compatible = "simple-bus";
129 			#address-cells = <2>;
130 			#size-cells = <2>;
131 			interrupt-parent = <&gic>;
135 			uart1: serial@400bc000 {
136 				compatible = "fsl,s32v234-linflexuart";