dts/freescale/s32g3.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3  * Copyright 2021-2024 NXP
7  *          Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 	interrupt-parent = <&gic>;
15 	#address-cells = <0x02>;
16 	#size-cells = <0x02>;
19 		#address-cells = <1>;
20 		#size-cells = <0>;
22 		cpu-map {
62 			compatible = "arm,cortex-a53";
64 			enable-method = "psci";
70 			compatible = "arm,cortex-a53";
72 			enable-method = "psci";
78 			compatible = "arm,cortex-a53";
80 			enable-method = "psci";
86 			compatible = "arm,cortex-a53";
88 			enable-method = "psci";
94 			compatible = "arm,cortex-a53";
96 			enable-method = "psci";
102 			compatible = "arm,cortex-a53";
104 			enable-method = "psci";
110 			compatible = "arm,cortex-a53";
112 			enable-method = "psci";
118 			compatible = "arm,cortex-a53";
120 			enable-method = "psci";
126 		scmi: scmi {  label
127 			compatible = "arm,scmi-smc";
129 			arm,smc-id = <0xc20000fe>;
130 			#address-cells = <1>;
131 			#size-cells = <0>;
135 				#clock-cells = <1>;
140 				#clock-cells = <1>;
145 			compatible = "arm,psci-1.0";
146 			method = "smc";
152 		compatible = "arm,cortex-a53-pmu";
156 	reserved-memory  {
157 		#address-cells = <2>;
158 		#size-cells = <2>;
162 			compatible = "arm,scmi-shmem";
164 			no-map;
169 		compatible = "simple-bus";
170 		#address-cells = <1>;
171 		#size-cells = <1>;
175 			compatible = "nxp,s32g2-siul2-pinctrl";
176 				/* MSCR0-MSCR101 registers on siul2_0 */
178 				/* MSCR112-MSCR122 registers on siul2_1 */
180 				/* MSCR144-MSCR190 registers on siul2_1 */
182 				/* IMCR0-IMCR83 registers on siul2_0 */
184 				/* IMCR119-IMCR397 registers on siul2_1 */
186 				/* IMCR430-IMCR495 registers on siul2_1 */
189 			jtag_pins: jtag-pins {
190 				jtag-grp0 {
192 					input-enable;
193 					bias-pull-up;
194 					slew-rate = <166>;
197 				jtag-grp1 {
199 					slew-rate = <166>;
202 				jtag-grp2 {
204 					input-enable;
205 					bias-pull-down;
206 					slew-rate = <166>;
209 				jtag-grp3 {
215 				jtag-grp4 {
217 					input-enable;
218 					bias-pull-up;
219 					slew-rate = <166>;
225 			compatible = "nxp,s32g3-linflexuart",
226 				     "fsl,s32v234-linflexuart";
233 			compatible = "nxp,s32g3-linflexuart",
234 				     "fsl,s32v234-linflexuart";
241 			compatible = "nxp,s32g3-linflexuart",
242 				     "fsl,s32v234-linflexuart";
249 			compatible = "nxp,s32g3-usdhc",
250 				     "nxp,s32g2-usdhc";
256 			clock-names = "ipg", "ahb", "per";
260 		gic: interrupt-controller@50800000 {
261 			compatible = "arm,gic-v3";
262 			#interrupt-cells = <3>;
263 			interrupt-controller;
274 		compatible = "arm,armv8-timer";
275 		interrupt-parent = <&gic>;
276 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
279 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
280 			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
281 		arm,no-tick-in-suspend;