dts/freescale/s32g2.dtsi

1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6  * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&gic>;
14 	#address-cells = <2>;
15 	#size-cells = <2>;
17 	reserved-memory  {
18 		#address-cells = <2>;
19 		#size-cells = <2>;
23 			compatible = "arm,scmi-shmem";
25 			no-map;
30 		#address-cells = <1>;
31 		#size-cells = <0>;
35 			compatible = "arm,cortex-a53";
37 			enable-method = "psci";
38 			next-level-cache = <&cluster0_l2>;
43 			compatible = "arm,cortex-a53";
45 			enable-method = "psci";
46 			next-level-cache = <&cluster0_l2>;
51 			compatible = "arm,cortex-a53";
53 			enable-method = "psci";
54 			next-level-cache = <&cluster1_l2>;
59 			compatible = "arm,cortex-a53";
61 			enable-method = "psci";
62 			next-level-cache = <&cluster1_l2>;
65 		cluster0_l2: l2-cache0 {
67 			cache-level = <2>;
68 			cache-unified;
71 		cluster1_l2: l2-cache1 {
73 			cache-level = <2>;
74 			cache-unified;
79 		compatible = "arm,cortex-a53-pmu";
84 		compatible = "arm,armv8-timer";
92 		scmi {
93 			compatible = "arm,scmi-smc";
94 			arm,smc-id = <0xc20000fe>;
95 			#address-cells = <1>;
96 			#size-cells = <0>;
101 				#clock-cells = <1>;
106 			compatible = "arm,psci-1.0";
107 			method = "smc";
112 		compatible = "simple-bus";
113 		#address-cells = <1>;
114 		#size-cells = <1>;
118 			compatible = "nxp,s32g2-siul2-pinctrl";
119 				/* MSCR0-MSCR101 registers on siul2_0 */
121 				/* MSCR112-MSCR122 registers on siul2_1 */
123 				/* MSCR144-MSCR190 registers on siul2_1 */
125 				/* IMCR0-IMCR83 registers on siul2_0 */
127 				/* IMCR119-IMCR397 registers on siul2_1 */
129 				/* IMCR430-IMCR495 registers on siul2_1 */
132 			jtag_pins: jtag-pins {
133 				jtag-grp0 {
135 					input-enable;
136 					bias-pull-up;
137 					slew-rate = <166>;
140 				jtag-grp1 {
142 					slew-rate = <166>;
145 				jtag-grp2 {
147 					input-enable;
148 					bias-pull-down;
149 					slew-rate = <166>;
152 				jtag-grp3 {
158 				jtag-grp4 {
160 					input-enable;
161 					bias-pull-up;
162 					slew-rate = <166>;
168 			compatible = "nxp,s32g2-linflexuart",
169 				     "fsl,s32v234-linflexuart";
176 			compatible = "nxp,s32g2-linflexuart",
177 				     "fsl,s32v234-linflexuart";
184 			compatible = "nxp,s32g2-linflexuart",
185 				     "fsl,s32v234-linflexuart";
192 			compatible = "nxp,s32g2-usdhc";
196 			clock-names = "ipg", "ahb", "per";
197 			bus-width = <8>;
201 		gic: interrupt-controller@50800000 {
202 			compatible = "arm,gic-v3";
209 			interrupt-controller;
210 			#interrupt-cells = <3>;