dts/freescale/imx8ulp.dtsi

35 		#size-cells = <0>;
37 		A35_0: cpu@0 {
40 			reg = <0x0 0x0>;
49 			reg = <0x0 0x1>;
66 				arm,psci-suspend-param = <0x0>;
77 		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
78 		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
101 			thermal-sensors = <&scmi_sensor 0>;
131 		#clock-cells = <0>;
138 		#clock-cells = <0>;
145 		#clock-cells = <0>;
152 		#clock-cells = <0>;
157 		reg = <0x0 0x2201f000 0x0 0x1000>;
161 		ranges = <0 0x0 0x2201f000 0x1000>;
163 		scmi_buf: scmi-sram-section@0 {
165 			reg = <0x0 0x400>;
172 			arm,smc-id = <0xc20000fe>;
174 			#size-cells = <0>;
178 				reg = <0x11>;
183 				reg = <0x15>;
194 	soc: soc@0 {
198 		ranges = <0x0 0x0 0x0 0x40000000>,
199 			 <0x60000000 0x0 0x60000000 0x1000000>;
203 			reg = <0x27020000 0x10000>;
210 			reg = <0x29000000 0x800000>;
217 				reg = <0x29220000 0x10000>;
225 				reg = <0x29230000 0x10000>;
234 				reg = <0x292a0000 0x10000>;
244 				reg = <0x292c0000 0x10000>;
250 				reg = <0x292d0000 0x10000>;
256 				compatible = "fsl,sec-v4.0";
257 				reg = <0x292e0000 0x10000>;
258 				ranges = <0 0x292e0000 0x10000>;
263 					compatible = "fsl,sec-v4.0-job-ring";
264 					reg = <0x1000 0x1000>;
269 					compatible = "fsl,sec-v4.0-job-ring";
270 					reg = <0x2000 0x1000>;
275 					compatible = "fsl,sec-v4.0-job-ring";
276 					reg = <0x3000 0x1000>;
281 					compatible = "fsl,sec-v4.0-job-ring";
282 					reg = <0x4000 0x1000>;
289 				reg = <0x29340000 0x1000>;
299 				reg = <0x29370000 0x10000>;
312 				reg = <0x29380000 0x10000>;
325 				reg = <0x29390000 0x1000>;
334 				reg = <0x293a0000 0x1000>;
343 				#size-cells = <0>;
345 				reg = <0x293b0000 0x10000>;
358 				#size-cells = <0>;
360 				reg = <0x293c0000 0x10000>;
374 			reg = <0x29800000 0x800000>;
381 				reg = <0x29800000 0x10000>;
388 				reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
391 				#size-cells = <0>;
403 				reg = <0x29840000 0x10000>;
416 				reg = <0x29850000 0x10000>;
429 				reg = <0x29860000 0x1000>;
438 				reg = <0x29870000 0x1000>;
447 				reg = <0x298c0000 0x10000>;
452 				reg = <0x298d0000 0x10000>;
461 				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
471 				reg = <0x298e0000 0x10000>;
480 				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
490 				reg = <0x298f0000 0x10000>;
499 				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
509 				reg = <0x29900000 0x200>;
514 				fsl,usbmisc = <&usbmisc1 0>;
515 				ahb-burst-config = <0x0>;
516 				tx-burst-size-dword = <0x8>;
517 				rx-burst-size-dword = <0x8>;
524 				reg = <0x29900200 0x200>;
531 				reg = <0x29910000 0x10000>;
534 				#phy-cells = <0>;
540 				reg = <0x29920000 0x200>;
545 				fsl,usbmisc = <&usbmisc2 0>;
546 				ahb-burst-config = <0x0>;
547 				tx-burst-size-dword = <0x8>;
548 				rx-burst-size-dword = <0x8>;
555 				reg = <0x29920200 0x200>;
562 				reg = <0x29930000 0x10000>;
565 				#phy-cells = <0>;
571 				reg = <0x29950000 0x10000>;
582 				reg = <0x2d000000 0x1000>;
592 				gpio-ranges = <&iomuxc1 0 32 24>;
597 				reg = <0x2d010000 0x1000>;
607 				gpio-ranges = <&iomuxc1 0 64 32>;
612 			reg = <0x2d800000 0x800000>;
619 				reg = <0x2da60000 0x10000>;
625 				reg = <0x2da70000 0x10000>;
633 			reg = <0x2e200000 0x1000>;
643 			gpio-ranges = <&iomuxc1 0 0 24>;