Lines Matching +full:fixed +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
27 vpu-core0 = &vpu_core0;
28 vpu-core1 = &vpu_core1;
29 vpu-core2 = &vpu_core2;
33 #address-cells = <2>;
34 #size-cells = <0>;
36 cpu-map {
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a53";
84 enable-method = "psci";
85 i-cache-size = <0x8000>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <256>;
88 d-cache-size = <0x8000>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <128>;
91 next-level-cache = <&A53_L2>;
92 operating-points-v2 = <&a53_opp_table>;
93 #cooling-cells = <2>;
98 compatible = "arm,cortex-a53";
101 enable-method = "psci";
102 i-cache-size = <0x8000>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <256>;
105 d-cache-size = <0x8000>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <128>;
108 next-level-cache = <&A53_L2>;
109 operating-points-v2 = <&a53_opp_table>;
110 #cooling-cells = <2>;
115 compatible = "arm,cortex-a53";
118 enable-method = "psci";
119 i-cache-size = <0x8000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <256>;
122 d-cache-size = <0x8000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&A53_L2>;
126 operating-points-v2 = <&a53_opp_table>;
127 #cooling-cells = <2>;
132 compatible = "arm,cortex-a72";
135 enable-method = "psci";
136 i-cache-size = <0xC000>;
137 i-cache-line-size = <64>;
138 i-cache-sets = <256>;
139 d-cache-size = <0x8000>;
140 d-cache-line-size = <64>;
141 d-cache-sets = <256>;
142 next-level-cache = <&A72_L2>;
143 operating-points-v2 = <&a72_opp_table>;
144 #cooling-cells = <2>;
149 compatible = "arm,cortex-a72";
152 enable-method = "psci";
153 next-level-cache = <&A72_L2>;
154 operating-points-v2 = <&a72_opp_table>;
155 #cooling-cells = <2>;
158 A53_L2: l2-cache0 {
160 cache-level = <2>;
161 cache-unified;
162 cache-size = <0x100000>;
163 cache-line-size = <64>;
164 cache-sets = <1024>;
167 A72_L2: l2-cache1 {
169 cache-level = <2>;
170 cache-unified;
171 cache-size = <0x100000>;
172 cache-line-size = <64>;
173 cache-sets = <1024>;
177 a53_opp_table: opp-table-0 {
178 compatible = "operating-points-v2";
179 opp-shared;
181 opp-600000000 {
182 opp-hz = /bits/ 64 <600000000>;
183 opp-microvolt = <900000>;
184 clock-latency-ns = <150000>;
187 opp-896000000 {
188 opp-hz = /bits/ 64 <896000000>;
189 opp-microvolt = <1000000>;
190 clock-latency-ns = <150000>;
193 opp-1104000000 {
194 opp-hz = /bits/ 64 <1104000000>;
195 opp-microvolt = <1100000>;
196 clock-latency-ns = <150000>;
199 opp-1200000000 {
200 opp-hz = /bits/ 64 <1200000000>;
201 opp-microvolt = <1100000>;
202 clock-latency-ns = <150000>;
203 opp-suspend;
207 a72_opp_table: opp-table-1 {
208 compatible = "operating-points-v2";
209 opp-shared;
211 opp-600000000 {
212 opp-hz = /bits/ 64 <600000000>;
213 opp-microvolt = <1000000>;
214 clock-latency-ns = <150000>;
217 opp-1056000000 {
218 opp-hz = /bits/ 64 <1056000000>;
219 opp-microvolt = <1000000>;
220 clock-latency-ns = <150000>;
223 opp-1296000000 {
224 opp-hz = /bits/ 64 <1296000000>;
225 opp-microvolt = <1100000>;
226 clock-latency-ns = <150000>;
229 opp-1596000000 {
230 opp-hz = /bits/ 64 <1596000000>;
231 opp-microvolt = <1100000>;
232 clock-latency-ns = <150000>;
233 opp-suspend;
237 gic: interrupt-controller@51a00000 {
238 compatible = "arm,gic-v3";
244 #interrupt-cells = <3>;
245 interrupt-controller;
247 interrupt-parent = <&gic>;
251 compatible = "arm,armv8-pmuv3";
256 compatible = "arm,psci-1.0";
261 compatible = "arm,armv8-timer";
263 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
269 compatible = "arm,mmu-500";
270 interrupt-parent = <&gic>;
272 #global-interrupts = <1>;
273 #iommu-cells = <2>;
309 system-controller {
310 compatible = "fsl,imx-scu";
311 mbox-names = "tx0",
318 pd: power-controller {
319 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
320 #power-domain-cells = <1>;
323 clk: clock-controller {
324 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
325 #clock-cells = <2>;
329 compatible = "fsl,imx8qm-iomuxc";
333 compatible = "fsl,imx8qxp-sc-rtc";
337 compatible = "fsl,imx8qm-scu-ocotp";
338 #address-cells = <1>;
339 #size-cells = <1>;
340 read-only;
351 tsens: thermal-sensor {
352 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
353 #thermal-sensor-cells = <1>;
357 thermal-zones {
358 cpu0-thermal {
359 polling-delay-passive = <250>;
360 polling-delay = <2000>;
361 thermal-sensors = <&tsens IMX_SC_R_A53>;
377 cooling-maps {
380 cooling-device =
389 cpu1-thermal {
390 polling-delay-passive = <250>;
391 polling-delay = <2000>;
392 thermal-sensors = <&tsens IMX_SC_R_A72>;
408 cooling-maps {
411 cooling-device =
418 gpu0-thermal {
419 polling-delay-passive = <250>;
420 polling-delay = <2000>;
421 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
438 gpu1-thermal {
439 polling-delay-passive = <250>;
440 polling-delay = <2000>;
441 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
458 drc0-thermal {
459 polling-delay-passive = <250>;
460 polling-delay = <2000>;
461 thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
479 clk_dummy: clock-dummy {
480 compatible = "fixed-clock";
481 #clock-cells = <0>;
482 clock-frequency = <0>;
483 clock-output-names = "clk_dummy";
486 clk_esai1_rx_clk: clock-esai1-rx {
487 compatible = "fixed-clock";
488 #clock-cells = <0>;
489 clock-frequency = <0>;
490 clock-output-names = "esai1_rx_clk";
493 clk_esai1_rx_hf_clk: clock-esai1-rx-hf {
494 compatible = "fixed-clock";
495 #clock-cells = <0>;
496 clock-frequency = <0>;
497 clock-output-names = "esai1_rx_hf_clk";
500 clk_esai1_tx_clk: clock-esai1-tx {
501 compatible = "fixed-clock";
502 #clock-cells = <0>;
503 clock-frequency = <0>;
504 clock-output-names = "esai1_tx_clk";
507 clk_esai1_tx_hf_clk: clock-esai1-tx-hf {
508 compatible = "fixed-clock";
509 #clock-cells = <0>;
510 clock-frequency = <0>;
511 clock-output-names = "esai1_tx_hf_clk";
514 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk {
515 compatible = "fixed-clock";
516 #clock-cells = <0>;
517 clock-frequency = <0>;
518 clock-output-names = "hdmi-rx-mclk";
521 clk_mlb_clk: clock-mlb-clk {
522 compatible = "fixed-clock";
523 #clock-cells = <0>;
524 clock-frequency = <0>;
525 clock-output-names = "mlb_clk";
528 clk_sai5_rx_bclk: clock-sai5-rx-bclk {
529 compatible = "fixed-clock";
530 #clock-cells = <0>;
531 clock-frequency = <0>;
532 clock-output-names = "sai5_rx_bclk";
535 clk_sai5_tx_bclk: clock-sai5-tx-bclk {
536 compatible = "fixed-clock";
537 #clock-cells = <0>;
538 clock-frequency = <0>;
539 clock-output-names = "sai5_tx_bclk";
542 clk_sai6_rx_bclk: clock-sai6-rx-bclk {
543 compatible = "fixed-clock";
544 #clock-cells = <0>;
545 clock-frequency = <0>;
546 clock-output-names = "sai6_rx_bclk";
549 clk_sai6_tx_bclk: clock-sai6-tx-bclk {
550 compatible = "fixed-clock";
551 #clock-cells = <0>;
552 clock-frequency = <0>;
553 clock-output-names = "sai6_tx_bclk";
556 clk_spdif1_rx: clock-spdif1-rx {
557 compatible = "fixed-clock";
558 #clock-cells = <0>;
559 clock-frequency = <0>;
560 clock-output-names = "spdif1_rx";
563 lvds_ipg_clk: clock-controller-lvds-ipg {
564 compatible = "fixed-clock";
565 #clock-cells = <0>;
566 clock-frequency = <24000000>;
567 clock-output-names = "lvds0_ipg_clk";
570 dsi_ipg_clk: clock-controller-dsi-ipg {
571 compatible = "fixed-clock";
572 #clock-cells = <0>;
573 clock-frequency = <120000000>;
574 clock-output-names = "dsi_ipg_clk";
577 mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
578 compatible = "fixed-clock";
579 #clock-cells = <0>;
580 clock-frequency = <432000000>;
581 clock-output-names = "mipi_pll_div2_clk";
585 #include "imx8-ss-cm41.dtsi"
586 #include "imx8-ss-audio.dtsi"
587 #include "imx8-ss-vpu.dtsi"
588 #include "imx8-ss-gpu0.dtsi"
589 #include "imx8-ss-mipi0.dtsi"
590 #include "imx8-ss-lvds0.dtsi"
591 #include "imx8-ss-mipi1.dtsi"
592 #include "imx8-ss-lvds1.dtsi"
593 #include "imx8-ss-img.dtsi"
594 #include "imx8-ss-dma.dtsi"
595 #include "imx8-ss-conn.dtsi"
596 #include "imx8-ss-lsio.dtsi"
599 #include "imx8qm-ss-img.dtsi"
600 #include "imx8qm-ss-dma.dtsi"
601 #include "imx8qm-ss-conn.dtsi"
602 #include "imx8qm-ss-lsio.dtsi"
603 #include "imx8qm-ss-audio.dtsi"
604 #include "imx8qm-ss-lvds.dtsi"
605 #include "imx8qm-ss-mipi.dtsi"