Lines Matching +full:imx +full:- +full:irqsteer
1 // SPDX-License-Identifier: GPL-2.0+
9 clock-indices = <IMX_LPCG_CLK_4>;
15 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
21 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
35 interrupt-parent = <&irqsteer_lvds0>;
37 irqsteer_lvds0: interrupt-controller@56240000 {
38 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
41 interrupt-controller;
42 interrupt-parent = <&gic>;
43 #interrupt-cells = <1>;
45 clock-names = "ipg";
46 power-domains = <&pd IMX_SC_R_LVDS_0>;
49 fsl,num-irqs = <32>;
52 lvds0_i2c1_lpcg: clock-controller@56243014 {
53 compatible = "fsl,imx8qxp-lpcg";
55 #clock-cells = <1>;
58 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
59 clock-output-names = "lvds0_i2c1_lpcg_clk",
61 power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
65 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
70 clock-names = "per", "ipg";
71 assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
72 assigned-clock-rates = <24000000>;
73 power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;