dts/freescale/imx8qm-ss-audio.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
7 /delete-node/ &acm;
8 /delete-node/ &sai4;
9 /delete-node/ &sai5;
10 /delete-node/ &sai4_lpcg;
11 /delete-node/ &sai5_lpcg;
37 	power-domains = <&pd IMX_SC_R_ASRC_0>;
43 	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>;
44 	clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk";
67 	power-domains = <&pd IMX_SC_R_ASRC_1>;
72 	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>;
73 	clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk";
79 		compatible = "fsl,imx8qm-sai";
87 		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
88 		dma-names = "rx";
91 		power-domains = <&pd IMX_SC_R_SAI_4>;
96 		compatible = "fsl,imx8qm-sai";
104 		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
105 		dma-names = "tx";
108 		power-domains = <&pd IMX_SC_R_SAI_5>;
112 	sai4_lpcg: clock-controller@59480000 {
113 		compatible = "fsl,imx8qxp-lpcg";
115 		#clock-cells = <1>;
118 		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
119 		clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk";
120 		power-domains = <&pd IMX_SC_R_SAI_4>;
124 	sai5_lpcg: clock-controller@59490000 {
125 		compatible = "fsl,imx8qxp-lpcg";
127 		#clock-cells = <1>;
130 		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
131 		clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk";
132 		power-domains = <&pd IMX_SC_R_SAI_5>;
137 		compatible = "fsl,imx8qm-esai";
144 		clock-names = "core", "extal", "fsys", "spba";
146 		dma-names = "rx", "tx";
147 		power-domains = <&pd IMX_SC_R_ESAI_1>;
152 		compatible = "fsl,imx8qm-sai";
160 		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
161 		dma-names = "rx", "tx";
163 		power-domains = <&pd IMX_SC_R_SAI_6>;
168 		compatible = "fsl,imx8qm-sai";
176 		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
177 		dma-names = "tx";
179 		power-domains = <&pd IMX_SC_R_SAI_7>;
183 	esai1_lpcg: clock-controller@59c10000 {
184 		compatible = "fsl,imx8qxp-lpcg";
186 		#clock-cells = <1>;
189 		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
190 		clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk";
191 		power-domains = <&pd IMX_SC_R_ESAI_1>;
194 	sai6_lpcg: clock-controller@59c20000 {
195 		compatible = "fsl,imx8qxp-lpcg";
197 		#clock-cells = <1>;
200 		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
201 		clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk";
202 		power-domains = <&pd IMX_SC_R_SAI_6>;
205 	sai7_lpcg: clock-controller@59c30000 {
206 		compatible = "fsl,imx8qxp-lpcg";
208 		#clock-cells = <1>;
211 		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
212 		clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk";
213 		power-domains = <&pd IMX_SC_R_SAI_7>;
217 		compatible = "fsl,imx8qm-acm";
219 		#clock-cells = <1>;
220 		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
268 		clock-names = "aud_rec_clk0_lpcg_clk",
309 	dma-channels = <20>;
310 	dma-channel-mask = <0>;
331 	power-domains = <&pd IMX_SC_R_DMA_2_CH0>,
356 	dma-channels = <11>;
357 	dma-channel-mask = <0xc0>;
369 	power-domains = <&pd IMX_SC_R_DMA_3_CH0>,
387 	power-domains = <&pd IMX_SC_R_ESAI_0>;
391 	clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
392 	clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk";
396 	clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
397 	clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk";
406 	power-domains = <&pd IMX_SC_R_SAI_0>;
410 	clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
411 	clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk";
420 	power-domains = <&pd IMX_SC_R_SAI_1>;
424 	clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
425 	clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk";
434 	power-domains = <&pd IMX_SC_R_SAI_2>;
438 	clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
439 	clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk";
448 	power-domains = <&pd IMX_SC_R_SAI_3>;
452 	clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>;
453 	clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk";
467 	power-domains = <&pd IMX_SC_R_SPDIF_0>;
471 	clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>;
472 	clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw";