Lines Matching +full:0 +full:x28000000
15 reg = <0x00000000 0x40000000 0 0x40000000>;
36 pinctrl-0 = <&pinctrl_dvfs>;
43 states = <900000 0x1 1000000 0x0>;
56 size = <0 0x28000000>;
58 alloc-ranges = <0 0x40000000 0 0x78000000>;
95 pinctrl-0 = <&pinctrl_i2c1>;
104 reg = <0x8>;
199 reg = <0x1b>;
204 reg = <0x51>;
206 pinctrl-0 = <&pinctrl_rtc>;
213 #clock-cells = <0>;
220 reg = <0x53>;
228 reg = <0x57>;
246 pinctrl-0 = <&pinctrl_qspi>;
251 flash0: flash@0 {
253 reg = <0>;
268 pinctrl-0 = <&pinctrl_usdhc1>;
287 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16>;
291 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f>,
292 <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f>;
296 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000074>,
297 <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000074>;
301 fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x97>,
302 <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
303 <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x97>,
304 <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x97>,
305 <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x97>,
306 <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x97>;
310 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41>;
314 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83>,
315 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3>,
316 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3>,
317 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3>,
318 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3>,
319 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3>,
320 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3>,
321 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3>,
322 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3>,
323 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3>,
324 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83>,
325 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
329 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85>,
330 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5>,
331 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5>,
332 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5>,
333 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5>,
334 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5>,
335 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5>,
336 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5>,
337 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5>,
338 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5>,
339 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85>,
340 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
344 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87>,
345 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7>,
346 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7>,
347 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7>,
348 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7>,
349 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7>,
350 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7>,
351 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7>,
352 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7>,
353 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7>,
354 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87>,
355 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
359 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;