Lines Matching +full:0 +full:x49
22 pwms = <&pwm1 0 5000000 0>;
23 brightness-levels = <0 100>;
27 default-brightness-level = <0>;
38 pinctrl-0 = <&pinctrl_gpio_keys>;
71 pwms = <&pwm2 0 50000 0>;
77 #clock-cells = <0>;
133 pinctrl-0 = <&pinctrl_pwr_en>;
144 #sound-dai-cells = <0>;
150 pinctrl-0 = <&pinctrl_micsel>;
158 pinctrl-0 = <&pinctrl_hpdet>;
208 pinctrl-0 = <&pinctrl_spkamp>;
217 pinctrl-0 = <&pinctrl_haptic>;
225 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
236 pinctrl-0 = <&pinctrl_usdhc2_rst>;
264 pinctrl-0 = <&pinctrl_fec1>;
273 #size-cells = <0>;
285 pinctrl-0 = <&pinctrl_i2c1>;
290 reg = <0x4b>;
292 pinctrl-0 = <&pinctrl_pmic>;
295 #clock-cells = <0>;
433 reg = <0x52>;
435 pinctrl-0 = <&pinctrl_typec>;
457 #size-cells = <0>;
459 port@0 {
460 reg = <0>;
480 reg = <0x68>;
482 pinctrl-0 = <&pinctrl_rtc>;
489 reg = <0x6b>;
491 pinctrl-0 = <&pinctrl_charger>;
507 pinctrl-0 = <&pinctrl_i2c3>;
512 reg = <0x1e>;
514 pinctrl-0 = <&pinctrl_imu>;
527 #sound-dai-cells = <0>;
528 reg = <0x0a>;
536 reg = <0x5d>;
538 pinctrl-0 = <&pinctrl_ts>;
540 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
542 irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
551 reg = <0x60>;
552 pinctrl-0 = <&pinctrl_prox>;
557 reg = <0x6a>;
560 mount-matrix = "1", "0", "0",
561 "0", "1", "0",
562 "0", "0", "-1";
569 MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */
575 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */
576 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */
582 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */
588 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
589 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
590 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
591 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
592 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
593 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
594 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
595 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
596 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
597 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
598 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
599 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
600 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
601 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
602 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
603 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
609 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */
610 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */
616 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
622 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
623 MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
624 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
630 MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */
636 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */
642 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
643 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
649 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
650 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
656 MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */
662 MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* MIC_SEL */
668 MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */
674 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */
680 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */
686 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
692 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */
698 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
699 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
700 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
701 MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
702 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
708 MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
709 MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
710 MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
711 MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
717 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
718 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
724 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
725 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
731 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
732 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
733 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
734 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
740 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
741 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
747 MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
748 MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
749 MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
750 MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
751 MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
757 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
758 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
759 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
760 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
761 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
762 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
763 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
764 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
765 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
766 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
767 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
768 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
774 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
775 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
776 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
777 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
778 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
779 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
780 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
781 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
782 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
783 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
784 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
785 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
791 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
792 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
793 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
794 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
795 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
796 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
797 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
798 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
799 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
800 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
801 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
802 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
808 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
814 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
820 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
821 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
822 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
823 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
824 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
825 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
831 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
832 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
833 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
834 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
835 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
836 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
842 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
843 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
844 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
845 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
846 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
847 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
853 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
859 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06
865 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */
866 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */
867 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */
879 #size-cells = <0>;
881 panel@0 {
883 reg = <0>;
915 pinctrl-0 = <&pinctrl_bl>;
921 pinctrl-0 = <&pinctrl_pwm_led>;
935 pinctrl-0 = <&pinctrl_sai2>;
944 pinctrl-0 = <&pinctrl_sai6>;
954 pinctrl-0 = <&pinctrl_uart1>;
960 pinctrl-0 = <&pinctrl_uart3>;
966 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
983 #size-cells = <0>;
987 port@0 {
988 reg = <0>;
1013 pinctrl-0 = <&pinctrl_usdhc1>;
1025 pinctrl-0 = <&pinctrl_usdhc2>;
1041 pinctrl-0 = <&pinctrl_wdog>;