Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci";
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>;
72 compatible = "arm,cortex-a53";
74 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <128>;
83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>;
90 compatible = "arm,cortex-a53";
92 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci";
95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci";
113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
124 A53_L2: l2-cache0 {
126 cache-unified;
127 cache-level = <2>;
128 cache-size = <0x80000>;
129 cache-line-size = <64>;
130 cache-sets = <512>;
134 a53_opp_table: opp-table {
135 compatible = "operating-points-v2";
136 opp-shared;
138 opp-1200000000 {
139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
146 opp-1600000000 {
147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <950000>;
149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <150000>;
151 opp-suspend;
154 opp-1800000000 {
155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <150000>;
159 opp-suspend;
163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k";
170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m";
177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1";
184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2";
191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3";
198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4";
207 * non-configurable funnel don't show up on the AMBA
210 compatible = "arm,coresight-static-funnel";
212 in-ports {
213 #address-cells = <1>;
214 #size-cells = <0>;
220 remote-endpoint = <&etm0_out_port>;
228 remote-endpoint = <&etm1_out_port>;
236 remote-endpoint = <&etm2_out_port>;
244 remote-endpoint = <&etm3_out_port>;
249 out-ports {
253 remote-endpoint = <&hugo_funnel_in_port0>;
259 reserved-memory {
260 #address-cells = <2>;
261 #size-cells = <2>;
266 no-map;
272 compatible = "arm,cortex-a53-pmu";
278 compatible = "arm,psci-1.0";
282 thermal-zones {
283 cpu-thermal {
284 polling-delay-passive = <250>;
285 polling-delay = <2000>;
286 thermal-sensors = <&tmu 0>;
301 cooling-maps {
304 cooling-device =
313 soc-thermal {
314 polling-delay-passive = <250>;
315 polling-delay = <2000>;
316 thermal-sensors = <&tmu 1>;
331 cooling-maps {
334 cooling-device =
345 compatible = "arm,armv8-timer";
350 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend;
355 compatible = "fsl,imx8mp-soc", "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <1>;
359 nvmem-cells = <&imx8mp_uid>;
360 nvmem-cell-names = "soc_unique_id";
363 compatible = "arm,coresight-etm4x", "arm,primecell";
366 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
367 clock-names = "apb_pclk";
369 out-ports {
372 remote-endpoint = <&ca_funnel_in_port0>;
379 compatible = "arm,coresight-etm4x", "arm,primecell";
382 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
383 clock-names = "apb_pclk";
385 out-ports {
388 remote-endpoint = <&ca_funnel_in_port1>;
395 compatible = "arm,coresight-etm4x", "arm,primecell";
398 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
399 clock-names = "apb_pclk";
401 out-ports {
404 remote-endpoint = <&ca_funnel_in_port2>;
411 compatible = "arm,coresight-etm4x", "arm,primecell";
414 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
415 clock-names = "apb_pclk";
417 out-ports {
420 remote-endpoint = <&ca_funnel_in_port3>;
427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
429 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
430 clock-names = "apb_pclk";
432 in-ports {
433 #address-cells = <1>;
434 #size-cells = <0>;
440 remote-endpoint = <&ca_funnel_out_port0>;
462 out-ports {
465 remote-endpoint = <&etf_in_port>;
472 compatible = "arm,coresight-tmc", "arm,primecell";
474 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
475 clock-names = "apb_pclk";
477 in-ports {
480 remote-endpoint = <&hugo_funnel_out_port0>;
485 out-ports {
488 remote-endpoint = <&etr_in_port>;
495 compatible = "arm,coresight-tmc", "arm,primecell";
497 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
498 clock-names = "apb_pclk";
500 in-ports {
503 remote-endpoint = <&etf_out_port>;
510 compatible = "fsl,aips-bus", "simple-bus";
512 #address-cells = <1>;
513 #size-cells = <1>;
517 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
521 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 gpio-ranges = <&iomuxc 0 5 30>;
530 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
534 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
535 gpio-controller;
536 #gpio-cells = <2>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 gpio-ranges = <&iomuxc 0 35 21>;
543 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
547 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
548 gpio-controller;
549 #gpio-cells = <2>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
556 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
560 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 gpio-ranges = <&iomuxc 0 82 32>;
569 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
573 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 gpio-ranges = <&iomuxc 0 114 30>;
582 compatible = "fsl,imx8mp-tmu";
584 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
585 nvmem-cells = <&tmu_calib>;
586 nvmem-cell-names = "calib";
587 #thermal-sensor-cells = <1>;
591 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
594 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
599 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
602 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
607 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
610 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
615 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
618 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
619 clock-names = "ipg", "per";
623 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
626 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
627 clock-names = "ipg", "per";
631 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
634 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
635 clock-names = "ipg", "per";
639 compatible = "fsl,imx8mp-iomuxc";
644 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
649 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
651 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
653 #address-cells = <1>;
654 #size-cells = <1>;
669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
673 cpu_speed_grade: speed-grade@10 { /* 0x440 */
677 eth_mac1: mac-address@90 { /* 0x640 */
681 eth_mac2: mac-address@96 { /* 0x658 */
685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
690 anatop: clock-controller@30360000 {
691 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
693 #clock-cells = <1>;
697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
700 snvs_rtc: snvs-rtc-lp {
701 compatible = "fsl,sec-v4.0-mon-rtc-lp";
706 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
707 clock-names = "snvs-rtc";
710 snvs_pwrkey: snvs-powerkey {
711 compatible = "fsl,sec-v4.0-pwrkey";
714 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
715 clock-names = "snvs-pwrkey";
717 wakeup-source;
721 snvs_lpgpr: snvs-lpgpr {
722 compatible = "fsl,imx8mp-snvs-lpgpr",
723 "fsl,imx7d-snvs-lpgpr";
727 clk: clock-controller@30380000 { label
728 compatible = "fsl,imx8mp-ccm";
732 #clock-cells = <1>;
735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 <&clk IMX8MP_CLK_A53_CORE>,
739 <&clk IMX8MP_CLK_NOC>,
740 <&clk IMX8MP_CLK_NOC_IO>,
741 <&clk IMX8MP_CLK_GIC>;
742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 <&clk IMX8MP_ARM_PLL_OUT>,
744 <&clk IMX8MP_SYS_PLL2_1000M>,
745 <&clk IMX8MP_SYS_PLL1_800M>,
746 <&clk IMX8MP_SYS_PLL2_500M>;
747 assigned-clock-rates = <0>, <0>,
753 src: reset-controller@30390000 { label
754 compatible = "fsl,imx8mp-src", "syscon";
757 #reset-cells = <1>;
761 compatible = "fsl,imx8mp-gpc";
763 interrupt-parent = <&gic>;
765 interrupt-controller;
766 #interrupt-cells = <3>;
769 #address-cells = <1>;
770 #size-cells = <0>;
772 pgc_mipi_phy1: power-domain@0 {
773 #power-domain-cells = <0>;
777 pgc_pcie_phy: power-domain@1 {
778 #power-domain-cells = <0>;
782 pgc_usb1_phy: power-domain@2 {
783 #power-domain-cells = <0>;
787 pgc_usb2_phy: power-domain@3 {
788 #power-domain-cells = <0>;
792 pgc_mlmix: power-domain@4 {
793 #power-domain-cells = <0>;
795 clocks = <&clk IMX8MP_CLK_ML_AXI>,
796 <&clk IMX8MP_CLK_ML_AHB>,
797 <&clk IMX8MP_CLK_NPU_ROOT>;
798 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
799 <&clk IMX8MP_CLK_ML_AXI>,
800 <&clk IMX8MP_CLK_ML_AHB>;
801 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
802 <&clk IMX8MP_SYS_PLL1_800M>,
803 <&clk IMX8MP_SYS_PLL1_800M>;
804 assigned-clock-rates = <800000000>,
809 pgc_audio: power-domain@5 {
810 #power-domain-cells = <0>;
812 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
813 <&clk IMX8MP_CLK_AUDIO_AXI>;
814 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
815 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
816 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
817 <&clk IMX8MP_SYS_PLL1_800M>;
818 assigned-clock-rates = <400000000>,
822 pgc_gpu2d: power-domain@6 {
823 #power-domain-cells = <0>;
825 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
826 power-domains = <&pgc_gpumix>;
829 pgc_gpumix: power-domain@7 {
830 #power-domain-cells = <0>;
832 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
833 <&clk IMX8MP_CLK_GPU_AHB>;
834 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
835 <&clk IMX8MP_CLK_GPU_AHB>;
836 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
837 <&clk IMX8MP_SYS_PLL1_800M>;
838 assigned-clock-rates = <800000000>, <400000000>;
841 pgc_vpumix: power-domain@8 {
842 #power-domain-cells = <0>;
844 clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
847 pgc_gpu3d: power-domain@9 {
848 #power-domain-cells = <0>;
850 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
851 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
852 power-domains = <&pgc_gpumix>;
855 pgc_mediamix: power-domain@10 {
856 #power-domain-cells = <0>;
858 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
859 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
862 pgc_vpu_g1: power-domain@11 {
863 #power-domain-cells = <0>;
864 power-domains = <&pgc_vpumix>;
866 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
869 pgc_vpu_g2: power-domain@12 {
870 #power-domain-cells = <0>;
871 power-domains = <&pgc_vpumix>;
873 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
877 pgc_vpu_vc8000e: power-domain@13 {
878 #power-domain-cells = <0>;
879 power-domains = <&pgc_vpumix>;
881 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
884 pgc_hdmimix: power-domain@14 {
885 #power-domain-cells = <0>;
887 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
888 <&clk IMX8MP_CLK_HDMI_APB>;
889 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
890 <&clk IMX8MP_CLK_HDMI_APB>;
891 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
892 <&clk IMX8MP_SYS_PLL1_133M>;
893 assigned-clock-rates = <500000000>, <133000000>;
896 pgc_hdmi_phy: power-domain@15 {
897 #power-domain-cells = <0>;
901 pgc_mipi_phy2: power-domain@16 {
902 #power-domain-cells = <0>;
906 pgc_hsiomix: power-domain@17 {
907 #power-domain-cells = <0>;
909 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
910 <&clk IMX8MP_CLK_HSIO_ROOT>;
911 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
912 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
913 assigned-clock-rates = <500000000>;
916 pgc_ispdwp: power-domain@18 {
917 #power-domain-cells = <0>;
919 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
926 compatible = "fsl,aips-bus", "simple-bus";
928 #address-cells = <1>;
929 #size-cells = <1>;
933 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
936 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
937 <&clk IMX8MP_CLK_PWM1_ROOT>;
938 clock-names = "ipg", "per";
939 #pwm-cells = <3>;
944 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
947 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
948 <&clk IMX8MP_CLK_PWM2_ROOT>;
949 clock-names = "ipg", "per";
950 #pwm-cells = <3>;
955 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
958 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
959 <&clk IMX8MP_CLK_PWM3_ROOT>;
960 clock-names = "ipg", "per";
961 #pwm-cells = <3>;
966 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
969 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
970 <&clk IMX8MP_CLK_PWM4_ROOT>;
971 clock-names = "ipg", "per";
972 #pwm-cells = <3>;
977 compatible = "nxp,sysctr-timer";
981 clock-names = "per";
985 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
988 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
989 clock-names = "ipg", "per";
993 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
996 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
997 clock-names = "ipg", "per";
1001 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1004 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
1005 clock-names = "ipg", "per";
1010 compatible = "fsl,aips-bus", "simple-bus";
1012 #address-cells = <1>;
1013 #size-cells = <1>;
1016 spba-bus@30800000 {
1017 compatible = "fsl,spba-bus", "simple-bus";
1019 #address-cells = <1>;
1020 #size-cells = <1>;
1023 ecspi1: spi@30820000 {
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1029 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1030 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1031 clock-names = "ipg", "per";
1032 assigned-clock-rates = <80000000>;
1033 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1034 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1036 dma-names = "rx", "tx";
1040 ecspi2: spi@30830000 {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1046 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1047 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1048 clock-names = "ipg", "per";
1049 assigned-clock-rates = <80000000>;
1050 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1051 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1053 dma-names = "rx", "tx";
1057 ecspi3: spi@30840000 {
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1063 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1064 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1065 clock-names = "ipg", "per";
1066 assigned-clock-rates = <80000000>;
1067 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1068 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1070 dma-names = "rx", "tx";
1075 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1078 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1079 <&clk IMX8MP_CLK_UART1_ROOT>;
1080 clock-names = "ipg", "per";
1082 dma-names = "rx", "tx";
1087 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1090 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1091 <&clk IMX8MP_CLK_UART3_ROOT>;
1092 clock-names = "ipg", "per";
1094 dma-names = "rx", "tx";
1099 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1102 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1103 <&clk IMX8MP_CLK_UART2_ROOT>;
1104 clock-names = "ipg", "per";
1106 dma-names = "rx", "tx";
1111 compatible = "fsl,imx8mp-flexcan";
1114 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1115 <&clk IMX8MP_CLK_CAN1_ROOT>;
1116 clock-names = "ipg", "per";
1117 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1118 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1119 assigned-clock-rates = <40000000>;
1120 fsl,clk-source = /bits/ 8 <0>;
1121 fsl,stop-mode = <&gpr 0x10 4>;
1126 compatible = "fsl,imx8mp-flexcan";
1129 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1130 <&clk IMX8MP_CLK_CAN2_ROOT>;
1131 clock-names = "ipg", "per";
1132 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1133 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1134 assigned-clock-rates = <40000000>;
1135 fsl,clk-source = /bits/ 8 <0>;
1136 fsl,stop-mode = <&gpr 0x10 5>;
1142 compatible = "fsl,sec-v4.0";
1143 #address-cells = <1>;
1144 #size-cells = <1>;
1148 clocks = <&clk IMX8MP_CLK_AHB>,
1149 <&clk IMX8MP_CLK_IPG_ROOT>;
1150 clock-names = "aclk", "ipg";
1153 compatible = "fsl,sec-v4.0-job-ring";
1160 compatible = "fsl,sec-v4.0-job-ring";
1166 compatible = "fsl,sec-v4.0-job-ring";
1173 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1178 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1183 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1184 #address-cells = <1>;
1185 #size-cells = <0>;
1188 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1193 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1198 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1203 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1208 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1213 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1216 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1217 <&clk IMX8MP_CLK_UART4_ROOT>;
1218 clock-names = "ipg", "per";
1220 dma-names = "rx", "tx";
1225 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1228 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1229 #mbox-cells = <2>;
1233 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1236 #mbox-cells = <2>;
1241 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1246 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1251 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1256 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1261 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1264 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1265 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1266 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1267 clock-names = "ipg", "ahb", "per";
1268 fsl,tuning-start-tap = <20>;
1269 fsl,tuning-step = <2>;
1270 bus-width = <4>;
1275 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1278 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1279 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1280 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1281 clock-names = "ipg", "ahb", "per";
1282 fsl,tuning-start-tap = <20>;
1283 fsl,tuning-step = <2>;
1284 bus-width = <4>;
1289 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1292 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1293 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1294 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1295 clock-names = "ipg", "ahb", "per";
1296 fsl,tuning-start-tap = <20>;
1297 fsl,tuning-step = <2>;
1298 bus-width = <4>;
1302 flexspi: spi@30bb0000 {
1303 compatible = "nxp,imx8mp-fspi";
1305 reg-names = "fspi_base", "fspi_mmap";
1307 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1308 <&clk IMX8MP_CLK_QSPI_ROOT>;
1309 clock-names = "fspi_en", "fspi";
1310 assigned-clock-rates = <80000000>;
1311 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1317 sdma1: dma-controller@30bd0000 {
1318 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1321 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1322 <&clk IMX8MP_CLK_AHB>;
1323 clock-names = "ipg", "ahb";
1324 #dma-cells = <3>;
1325 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1329 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1335 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1336 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1337 <&clk IMX8MP_CLK_ENET_TIMER>,
1338 <&clk IMX8MP_CLK_ENET_REF>,
1339 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1340 clock-names = "ipg", "ahb", "ptp",
1342 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1343 <&clk IMX8MP_CLK_ENET_TIMER>,
1344 <&clk IMX8MP_CLK_ENET_REF>,
1345 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1346 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1347 <&clk IMX8MP_SYS_PLL2_100M>,
1348 <&clk IMX8MP_SYS_PLL2_125M>,
1349 <&clk IMX8MP_SYS_PLL2_50M>;
1350 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,num-tx-queues = <3>;
1352 fsl,num-rx-queues = <3>;
1353 nvmem-cells = <ð_mac1>;
1354 nvmem-cell-names = "mac-address";
1355 fsl,stop-mode = <&gpr 0x10 3>;
1360 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1364 interrupt-names = "macirq", "eth_wake_irq";
1365 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1366 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1367 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1368 <&clk IMX8MP_CLK_ENET_QOS>;
1369 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1370 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1371 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1372 <&clk IMX8MP_CLK_ENET_QOS>;
1373 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1374 <&clk IMX8MP_SYS_PLL2_100M>,
1375 <&clk IMX8MP_SYS_PLL2_125M>;
1376 assigned-clock-rates = <0>, <100000000>, <125000000>;
1377 nvmem-cells = <ð_mac2>;
1378 nvmem-cell-names = "mac-address";
1385 compatible = "fsl,aips-bus", "simple-bus";
1387 #address-cells = <1>;
1388 #size-cells = <1>;
1391 spba-bus@30c00000 {
1392 compatible = "fsl,spba-bus", "simple-bus";
1394 #address-cells = <1>;
1395 #size-cells = <1>;
1399 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1401 #sound-dai-cells = <0>;
1403 <&clk IMX8MP_CLK_DUMMY>,
1407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1409 dma-names = "rx", "tx";
1415 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1417 #sound-dai-cells = <0>;
1419 <&clk IMX8MP_CLK_DUMMY>,
1423 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1425 dma-names = "rx", "tx";
1431 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1433 #sound-dai-cells = <0>;
1435 <&clk IMX8MP_CLK_DUMMY>,
1439 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1441 dma-names = "rx", "tx";
1447 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1449 #sound-dai-cells = <0>;
1451 <&clk IMX8MP_CLK_DUMMY>,
1455 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1457 dma-names = "rx", "tx";
1463 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1465 #sound-dai-cells = <0>;
1467 <&clk IMX8MP_CLK_DUMMY>,
1471 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1473 dma-names = "rx", "tx";
1479 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1481 #sound-dai-cells = <0>;
1483 <&clk IMX8MP_CLK_DUMMY>,
1487 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1489 dma-names = "rx", "tx";
1495 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1499 clock-names = "mem";
1504 dma-names = "ctx0_rx", "ctx0_tx",
1508 firmware-name = "imx/easrc/easrc-imx8mn.bin";
1509 fsl,asrc-rate = <8000>;
1510 fsl,asrc-format = <2>;
1514 micfil: audio-controller@30ca0000 {
1515 compatible = "fsl,imx8mp-micfil";
1517 #sound-dai-cells = <0>;
1524 <&clk IMX8MP_AUDIO_PLL1_OUT>,
1525 <&clk IMX8MP_AUDIO_PLL2_OUT>,
1526 <&clk IMX8MP_CLK_EXT3>;
1527 clock-names = "ipg_clk", "ipg_clk_app",
1530 dma-names = "rx";
1535 compatible = "fsl,imx8mp-aud2htx";
1539 clock-names = "bus";
1541 dma-names = "tx";
1546 compatible = "fsl,imx8mp-xcvr";
1551 reg-names = "ram", "regs", "rxfifo",
1557 /* XCVR PHY - SPDIF wakeup IRQ */
1563 clock-names = "ipg", "phy", "spba", "pll_ipg";
1565 dma-names = "rx", "tx";
1571 sdma3: dma-controller@30e00000 {
1572 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1574 #dma-cells = <3>;
1576 <&clk IMX8MP_CLK_AUDIO_ROOT>;
1577 clock-names = "ipg", "ahb";
1579 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1582 sdma2: dma-controller@30e10000 {
1583 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1585 #dma-cells = <3>;
1587 <&clk IMX8MP_CLK_AUDIO_ROOT>;
1588 clock-names = "ipg", "ahb";
1590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1593 audio_blk_ctrl: clock-controller@30e20000 {
1594 compatible = "fsl,imx8mp-audio-blk-ctrl";
1596 #clock-cells = <1>;
1597 #reset-cells = <1>;
1598 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
1599 <&clk IMX8MP_CLK_SAI1>,
1600 <&clk IMX8MP_CLK_SAI2>,
1601 <&clk IMX8MP_CLK_SAI3>,
1602 <&clk IMX8MP_CLK_SAI5>,
1603 <&clk IMX8MP_CLK_SAI6>,
1604 <&clk IMX8MP_CLK_SAI7>;
1605 clock-names = "ahb",
1608 power-domains = <&pgc_audio>;
1609 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
1610 <&clk IMX8MP_AUDIO_PLL2>;
1611 assigned-clock-rates = <393216000>, <361267200>;
1616 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1618 clocks = <&clk IMX8MP_CLK_NOC>;
1619 #interconnect-cells = <1>;
1620 operating-points-v2 = <&noc_opp_table>;
1622 noc_opp_table: opp-table {
1623 compatible = "operating-points-v2";
1625 opp-200000000 {
1626 opp-hz = /bits/ 64 <200000000>;
1629 opp-1000000000 {
1630 opp-hz = /bits/ 64 <1000000000>;
1636 compatible = "fsl,aips-bus", "simple-bus";
1638 #address-cells = <1>;
1639 #size-cells = <1>;
1643 compatible = "fsl,imx8mp-isi";
1647 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1648 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1649 clock-names = "axi", "apb";
1650 fsl,blk-ctrl = <&media_blk_ctrl>;
1651 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1662 remote-endpoint = <&mipi_csi_0_out>;
1670 remote-endpoint = <&mipi_csi_1_out>;
1677 compatible = "fsl,imx8mp-isp";
1680 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1681 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1682 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1683 clock-names = "isp", "aclk", "hclk";
1684 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1685 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1699 compatible = "fsl,imx8mp-isp";
1702 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1703 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1704 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1705 clock-names = "isp", "aclk", "hclk";
1706 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1707 fsl,blk-ctrl = <&media_blk_ctrl 1>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1721 compatible = "nxp,imx8mp-dw100";
1724 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1725 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1726 clock-names = "axi", "ahb";
1727 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1731 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1734 clock-frequency = <250000000>;
1735 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1736 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1737 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1738 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1739 clock-names = "pclk", "wrap", "phy", "axi";
1740 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1741 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1743 <&clk IMX8MP_CLK_24M>;
1744 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1748 #address-cells = <1>;
1749 #size-cells = <0>;
1759 remote-endpoint = <&isi_in_0>;
1766 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1769 clock-frequency = <250000000>;
1770 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1771 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1772 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1773 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1774 clock-names = "pclk", "wrap", "phy", "axi";
1775 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1776 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1777 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1778 <&clk IMX8MP_CLK_24M>;
1779 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1783 #address-cells = <1>;
1784 #size-cells = <0>;
1794 remote-endpoint = <&isi_in_1>;
1801 compatible = "fsl,imx8mp-mipi-dsim";
1803 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1804 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1805 clock-names = "bus_clk", "sclk_mipi";
1806 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1807 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1808 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1809 <&clk IMX8MP_CLK_24M>;
1810 assigned-clock-rates = <200000000>, <24000000>;
1811 samsung,pll-clock-frequency = <24000000>;
1813 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1824 remote-endpoint = <&lcdif1_to_dsim>;
1837 lcdif1: display-controller@32e80000 {
1838 compatible = "fsl,imx8mp-lcdif";
1840 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1841 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1842 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1843 clock-names = "pix", "axi", "disp_axi";
1845 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1850 remote-endpoint = <&dsim_from_lcdif1>;
1855 lcdif2: display-controller@32e90000 {
1856 compatible = "fsl,imx8mp-lcdif";
1859 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1860 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1861 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1862 clock-names = "pix", "axi", "disp_axi";
1863 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1868 remote-endpoint = <&ldb_from_lcdif2>;
1873 media_blk_ctrl: blk-ctrl@32ec0000 {
1874 compatible = "fsl,imx8mp-media-blk-ctrl",
1877 #address-cells = <1>;
1878 #size-cells = <1>;
1879 power-domains = <&pgc_mediamix>,
1889 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1890 "lcdif1", "isi", "mipi-csi2",
1892 "mipi-dsi2";
1902 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1905 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1906 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1907 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1908 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1909 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1910 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1911 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1912 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1913 clock-names = "apb", "axi", "cam1", "cam2",
1922 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1923 <&clk IMX8MP_CLK_MEDIA_APB>,
1924 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
1925 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
1926 <&clk IMX8MP_CLK_MEDIA_ISP>,
1927 <&clk IMX8MP_VIDEO_PLL1>;
1928 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1929 <&clk IMX8MP_SYS_PLL1_800M>,
1930 <&clk IMX8MP_VIDEO_PLL1_OUT>,
1931 <&clk IMX8MP_VIDEO_PLL1_OUT>,
1932 <&clk IMX8MP_SYS_PLL2_500M>;
1933 assigned-clock-rates = <500000000>, <200000000>,
1936 #power-domain-cells = <1>;
1939 compatible = "fsl,imx8mp-ldb";
1941 reg-names = "ldb", "lvds";
1942 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>;
1943 clock-names = "ldb";
1944 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1945 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1949 #address-cells = <1>;
1950 #size-cells = <0>;
1956 remote-endpoint = <&lcdif2_to_ldb>;
1977 pcie_phy: pcie-phy@32f00000 {
1978 compatible = "fsl,imx8mp-pcie-phy";
1980 resets = <&src IMX8MP_RESET_PCIEPHY>,
1981 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1982 reset-names = "pciephy", "perst";
1983 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1984 #phy-cells = <0>;
1988 hsio_blk_ctrl: blk-ctrl@32f10000 {
1989 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1991 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1992 <&clk IMX8MP_CLK_PCIE_ROOT>;
1993 clock-names = "usb", "pcie";
1994 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1997 power-domain-names = "bus", "usb", "usb-phy1",
1998 "usb-phy2", "pcie", "pcie-phy";
2003 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2004 #power-domain-cells = <1>;
2005 #clock-cells = <0>;
2008 hdmi_blk_ctrl: blk-ctrl@32fc0000 {
2009 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
2011 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
2012 <&clk IMX8MP_CLK_HDMI_ROOT>,
2013 <&clk IMX8MP_CLK_HDMI_REF_266M>,
2014 <&clk IMX8MP_CLK_HDMI_24M>,
2015 <&clk IMX8MP_CLK_HDMI_FDCC_TST>;
2016 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
2017 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
2022 power-domain-names = "bus", "irqsteer", "lcdif",
2024 "hdmi-tx", "hdmi-tx-phy",
2026 #power-domain-cells = <1>;
2029 irqsteer_hdmi: interrupt-controller@32fc2000 {
2030 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
2033 interrupt-controller;
2034 #interrupt-cells = <1>;
2036 fsl,num-irqs = <64>;
2037 clocks = <&clk IMX8MP_CLK_HDMI_APB>;
2038 clock-names = "ipg";
2039 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
2042 hdmi_pvi: display-bridge@32fc4000 {
2043 compatible = "fsl,imx8mp-hdmi-pvi";
2045 interrupt-parent = <&irqsteer_hdmi>;
2047 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
2051 #address-cells = <1>;
2052 #size-cells = <0>;
2057 remote-endpoint = <&lcdif3_to_pvi>;
2064 remote-endpoint = <&hdmi_tx_from_pvi>;
2070 lcdif3: display-controller@32fc6000 {
2071 compatible = "fsl,imx8mp-lcdif";
2073 interrupt-parent = <&irqsteer_hdmi>;
2076 <&clk IMX8MP_CLK_HDMI_APB>,
2077 <&clk IMX8MP_CLK_HDMI_ROOT>;
2078 clock-names = "pix", "axi", "disp_axi";
2079 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
2084 remote-endpoint = <&pvi_from_lcdif3>;
2090 compatible = "fsl,imx8mp-hdmi-tx";
2092 interrupt-parent = <&irqsteer_hdmi>;
2094 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
2095 <&clk IMX8MP_CLK_HDMI_REF_266M>,
2096 <&clk IMX8MP_CLK_32K>,
2098 clock-names = "iahb", "isfr", "cec", "pix";
2099 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
2100 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
2101 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
2102 reg-io-width = <1>;
2106 #address-cells = <1>;
2107 #size-cells = <0>;
2113 remote-endpoint = <&pvi_to_hdmi_tx>;
2125 compatible = "fsl,imx8mp-hdmi-phy";
2127 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
2128 <&clk IMX8MP_CLK_HDMI_24M>;
2129 clock-names = "apb", "ref";
2130 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
2131 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2132 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
2133 #clock-cells = <0>;
2134 #phy-cells = <0>;
2140 compatible = "fsl,imx8mp-pcie";
2142 reg-names = "dbi", "config";
2143 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2144 <&clk IMX8MP_CLK_HSIO_AXI>,
2145 <&clk IMX8MP_CLK_PCIE_ROOT>;
2146 clock-names = "pcie", "pcie_bus", "pcie_aux";
2147 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2148 assigned-clock-rates = <10000000>;
2149 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2150 #address-cells = <3>;
2151 #size-cells = <2>;
2153 bus-range = <0x00 0xff>;
2155 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2156 num-lanes = <1>;
2157 num-viewport = <4>;
2159 interrupt-names = "msi";
2160 #interrupt-cells = <1>;
2161 interrupt-map-mask = <0 0 0 0x7>;
2162 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2166 fsl,max-link-speed = <3>;
2167 linux,pci-domain = <0>;
2168 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2169 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
2170 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
2171 reset-names = "apps", "turnoff";
2173 phy-names = "pcie-phy";
2177 pcie_ep: pcie-ep@33800000 {
2178 compatible = "fsl,imx8mp-pcie-ep";
2180 reg-names = "dbi", "addr_space";
2181 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2182 <&clk IMX8MP_CLK_HSIO_AXI>,
2183 <&clk IMX8MP_CLK_PCIE_ROOT>;
2184 clock-names = "pcie", "pcie_bus", "pcie_aux";
2185 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2186 assigned-clock-rates = <10000000>;
2187 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2188 num-lanes = <1>;
2190 interrupt-names = "dma";
2191 fsl,max-link-speed = <3>;
2192 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2193 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
2194 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
2195 reset-names = "apps", "turnoff";
2197 phy-names = "pcie-phy";
2198 num-ib-windows = <4>;
2199 num-ob-windows = <4>;
2207 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
2208 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
2209 <&clk IMX8MP_CLK_GPU_ROOT>,
2210 <&clk IMX8MP_CLK_GPU_AHB>;
2211 clock-names = "core", "shader", "bus", "reg";
2212 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2213 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
2214 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
2215 <&clk IMX8MP_SYS_PLL1_800M>;
2216 assigned-clock-rates = <800000000>, <800000000>;
2217 power-domains = <&pgc_gpu3d>;
2224 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
2225 <&clk IMX8MP_CLK_GPU_ROOT>,
2226 <&clk IMX8MP_CLK_GPU_AHB>;
2227 clock-names = "core", "bus", "reg";
2228 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2229 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2230 assigned-clock-rates = <800000000>;
2231 power-domains = <&pgc_gpu2d>;
2234 vpu_g1: video-codec@38300000 {
2235 compatible = "nxp,imx8mm-vpu-g1";
2238 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
2239 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
2240 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2241 assigned-clock-rates = <600000000>;
2242 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
2245 vpu_g2: video-codec@38310000 {
2246 compatible = "nxp,imx8mq-vpu-g2";
2249 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
2250 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
2251 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
2252 assigned-clock-rates = <500000000>;
2253 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
2256 vpumix_blk_ctrl: blk-ctrl@38330000 {
2257 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2259 #power-domain-cells = <1>;
2260 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2262 power-domain-names = "bus", "g1", "g2", "vc8000e";
2263 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
2264 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
2265 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
2266 clock-names = "g1", "g2", "vc8000e";
2267 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
2268 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2269 assigned-clock-rates = <600000000>, <600000000>;
2273 interconnect-names = "g1", "g2", "vc8000e";
2280 clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
2281 <&clk IMX8MP_CLK_NPU_ROOT>,
2282 <&clk IMX8MP_CLK_ML_AXI>,
2283 <&clk IMX8MP_CLK_ML_AHB>;
2284 clock-names = "core", "shader", "bus", "reg";
2285 power-domains = <&pgc_mlmix>;
2288 gic: interrupt-controller@38800000 {
2289 compatible = "arm,gic-v3";
2292 #interrupt-cells = <3>;
2293 interrupt-controller;
2295 interrupt-parent = <&gic>;
2298 edacmc: memory-controller@3d400000 {
2299 compatible = "snps,ddrc-3.80a";
2304 ddr-pmu@3d800000 {
2305 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2310 usb3_phy0: usb-phy@381f0040 {
2311 compatible = "fsl,imx8mp-usb-phy";
2313 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2314 clock-names = "phy";
2315 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2316 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2317 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2318 #phy-cells = <0>;
2323 compatible = "fsl,imx8mp-dwc3";
2326 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2327 <&clk IMX8MP_CLK_USB_SUSP>;
2328 clock-names = "hsio", "suspend";
2330 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2331 #address-cells = <1>;
2332 #size-cells = <1>;
2333 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2340 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2341 <&clk IMX8MP_CLK_USB_CORE_REF>,
2342 <&clk IMX8MP_CLK_USB_SUSP>;
2343 clock-names = "bus_early", "ref", "suspend";
2346 phy-names = "usb2-phy", "usb3-phy";
2347 snps,gfladj-refclk-lpm-sel-quirk;
2348 snps,parkmode-disable-ss-quirk;
2353 usb3_phy1: usb-phy@382f0040 {
2354 compatible = "fsl,imx8mp-usb-phy";
2356 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2357 clock-names = "phy";
2358 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2359 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2360 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2361 #phy-cells = <0>;
2366 compatible = "fsl,imx8mp-dwc3";
2369 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2370 <&clk IMX8MP_CLK_USB_SUSP>;
2371 clock-names = "hsio", "suspend";
2373 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2374 #address-cells = <1>;
2375 #size-cells = <1>;
2376 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2383 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2384 <&clk IMX8MP_CLK_USB_CORE_REF>,
2385 <&clk IMX8MP_CLK_USB_SUSP>;
2386 clock-names = "bus_early", "ref", "suspend";
2389 phy-names = "usb2-phy", "usb3-phy";
2390 snps,gfladj-refclk-lpm-sel-quirk;
2391 snps,parkmode-disable-ss-quirk;
2396 compatible = "fsl,imx8mp-dsp";
2398 mbox-names = "txdb0", "txdb1",
2402 memory-region = <&dsp_reserved>;