Lines Matching +full:pinctrl +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include <dt-bindings/pwm/pwm.h>
15 #include "imx8mp-tqma8mpql.dtsi"
18 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
19 compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
20 chassis-type = "embedded";
23 stdout-path = &uart4;
36 compatible = "pwm-backlight";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_backlight>;
39 pwms = <&pwm2 0 5000000 0>;
40 brightness-levels = <0 4 8 16 32 64 128 255>;
41 default-brightness-level = <7>;
42 power-supply = <®_vcc_12v0>;
43 enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_lvdsdisplay>;
55 power-supply = <®_vcc_3v3>;
56 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
61 gpio-leds {
62 compatible = "gpio-leds";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_gpioled>;
66 led-1 {
69 function-enumerator = <0>;
73 led-2 {
76 function-enumerator = <1>;
81 hdmi-connector {
82 compatible = "hdmi-connector";
88 remote-endpoint = <&hdmi_tx_out>;
93 reg_usdhc2_vmmc: regulator-usdhc2 {
94 compatible = "regulator-fixed";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
97 regulator-name = "VSD_3V3";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
101 enable-active-high;
102 startup-delay-us = <100>;
103 off-on-delay-us = <12000>;
106 reg_vcc_3v3: regulator-3v3 {
107 compatible = "regulator-fixed";
108 regulator-name = "V_3V3";
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
113 reg_vcc_5v0: regulator-5v0 {
114 compatible = "regulator-fixed";
115 regulator-name = "V_5V0";
116 regulator-min-microvolt = <5000000>;
117 regulator-max-microvolt = <5000000>;
120 reg_vcc_12v0: regulator-12v0 {
121 compatible = "regulator-fixed";
122 regulator-name = "V_12V";
123 regulator-min-microvolt = <12000000>;
124 regulator-max-microvolt = <12000000>;
127 reserved-memory {
128 #address-cells = <2>;
129 #size-cells = <2>;
134 compatible = "shared-dma-pool";
136 size = <0 0x38000000>;
137 alloc-ranges = <0 0x40000000 0 0xB0000000>;
138 linux,cma-default;
143 compatible = "rfkill-gpio";
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_rfkill>;
146 label = "rfkill-pcie-wlan";
147 radio-type = "wlan";
148 shutdown-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
152 compatible = "fsl,imx-audio-tlv320aic32x4";
153 model = "tq-mba8mp-ras314";
154 audio-cpu = <&sai5>;
155 audio-codec = <&tlv320aic3x04>;
156 audio-routing =
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_ecspi3>;
167 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio1 6 GPIO_ACTIVE_LOW>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_eqos>;
174 phy-mode = "rgmii-id";
175 phy-handle = <ðphy3>;
179 compatible = "snps,dwmac-mdio";
180 #address-cells = <1>;
181 #size-cells = <0>;
183 ethphy3: ethernet-phy@3 {
184 compatible = "ethernet-phy-ieee802.3-c22";
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_eqos_phy>;
188 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
189 reset-assert-us = <500000>;
190 reset-deassert-us = <50000>;
191 enet-phy-lane-no-swap;
192 interrupt-parent = <&gpio4>;
194 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
195 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
196 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
197 ti,dp83867-rxctrl-strap-quirk;
198 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_fec>;
206 phy-mode = "rgmii-id";
207 phy-handle = <ðphy0>;
208 fsl,magic-packet;
212 #address-cells = <1>;
213 #size-cells = <0>;
215 ethphy0: ethernet-phy@0 {
216 compatible = "ethernet-phy-ieee802.3-c22";
217 reg = <0>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_fec_phy>;
220 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
221 reset-assert-us = <500000>;
222 reset-deassert-us = <50000>;
223 enet-phy-lane-no-swap;
224 interrupt-parent = <&gpio4>;
226 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
227 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
228 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
229 ti,dp83867-rxctrl-strap-quirk;
230 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_gpio1>;
239 gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "",
248 wifi-pmic-en-hog {
249 gpio-hog;
250 gpios = <0 0>;
251 output-high;
252 line-name = "WIFI_PMIC_EN";
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_gpio2>;
260 gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25",
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_gpio3>;
274 gpio-line-names = "", "", "", "",
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_gpio4>;
288 gpio-line-names = "", "", "", "",
297 pewake-hog {
298 gpio-hog;
299 gpios = <25 0>;
301 line-name = "PCIE_WAKE#";
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpt1_gpio>,
310 gpio-line-names = "", "GPIO18", "", "GPIO3",
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_gpt1>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_gpt2>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_gpt3>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_hdmi>;
350 remote-endpoint = <&hdmi_connector_in>;
362 clock-frequency = <384000>;
363 pinctrl-names = "default", "gpio";
364 pinctrl-0 = <&pinctrl_i2c2>;
365 pinctrl-1 = <&pinctrl_i2c2_gpio>;
366 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
367 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
373 clock-frequency = <384000>;
374 pinctrl-names = "default", "gpio";
375 pinctrl-0 = <&pinctrl_i2c3>;
376 pinctrl-1 = <&pinctrl_i2c3_gpio>;
377 scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
378 sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
383 clock-frequency = <384000>;
384 pinctrl-names = "default", "gpio";
385 pinctrl-0 = <&pinctrl_i2c4>;
386 pinctrl-1 = <&pinctrl_i2c4_gpio>;
387 scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
388 sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
391 tlv320aic3x04: audio-codec@18 {
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_tlv320aic3x04>;
395 reg = <0x18>;
396 clock-names = "mclk";
398 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
399 iov-supply = <®_vcc_3v3>;
400 ldoin-supply = <®_vcc_3v3>;
406 clock-frequency = <384000>;
407 pinctrl-names = "default", "gpio";
408 pinctrl-0 = <&pinctrl_i2c5>;
409 pinctrl-1 = <&pinctrl_i2c5_gpio>;
410 scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
411 sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
417 clock-frequency = <384000>;
418 pinctrl-names = "default", "gpio";
419 pinctrl-0 = <&pinctrl_i2c6>;
420 pinctrl-1 = <&pinctrl_i2c6_gpio>;
421 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
422 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
431 /* RTC_EVENT# is connected on MBa8MP-RAS314 */
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_pcf85063>;
434 interrupt-parent = <&gpio3>;
440 clock-names = "ref";
441 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&pinctrl_pcie>;
448 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_pwm2>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_pwm3>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_pwm4>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_sai5>;
473 assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
474 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
475 assigned-clock-rates = <12288000>;
476 fsl,sai-mclk-direction-output;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_uart1>;
488 uart-has-rtscts;
489 assigned-clocks = <&clk IMX8MP_CLK_UART1>;
490 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_uart2>;
497 uart-has-rtscts;
498 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
499 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
503 compatible = "nxp,88w8987-bt";
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_uart3>;
510 assigned-clocks = <&clk IMX8MP_CLK_UART3>;
511 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_uart4>;
523 fsl,disable-port-power-control;
528 fsl,disable-port-power-control;
529 fsl,permanently-attached;
534 vbus-supply = <®_vcc_5v0>;
539 vbus-supply = <®_vcc_5v0>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_usbhub>;
559 peer-hub = <&hub_3_0>;
560 reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
561 vdd-supply = <®_vcc_3v3>;
567 peer-hub = <&hub_2_0>;
568 reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
569 vdd-supply = <®_vcc_3v3>;
573 /* X1 SD card on GPIO22-GPIO27 */
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_usdhc1>;
577 disable-wp;
578 bus-width = <4>;
583 pinctrl-names = "default", "state_100mhz", "state_200mhz";
584 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
585 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
586 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
587 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
588 vmmc-supply = <®_usdhc2_vmmc>;
589 no-mmc;
590 no-sdio;
591 disable-wp;
592 bus-width = <4>;
598 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x14>;
602 fsl,pins = <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x140>,
603 <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x140>,
604 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>,
605 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x140>,
606 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140>;
610 fsl,pins = <MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x80>,
611 <MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x80>,
612 <MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x80>,
613 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x80>,
614 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x80>;
618 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>,
619 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>,
620 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>,
621 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>,
622 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>,
623 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>,
624 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>,
625 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>,
626 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>,
627 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>,
628 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>,
629 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>,
630 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>,
631 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>;
635 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>,
636 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>;
640 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>,
641 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>,
642 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>,
643 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>,
644 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>,
645 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>,
646 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>,
647 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>,
648 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>,
649 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>,
650 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>,
651 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>,
652 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>,
653 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>;
657 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>,
658 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>;
662 fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x14>,
663 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x14>;
667 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x14>,
668 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x14>;
672 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x94>,
673 <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x94>,
674 <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x94>,
675 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x94>,
676 <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x94>,
677 <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x94>,
678 <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x94>,
679 <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x94>;
683 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x180>;
687 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x80>,
689 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>,
690 <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x94>,
691 <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x94>;
695 fsl,pins = <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x80>,
696 <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x80>;
700 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
701 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
702 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>,
703 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>;
707 fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x14>;
711 fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x80>;
715 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x14>;
719 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>;
723 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x14>;
727 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x80>;
731 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>,
732 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>;
735 pinctrl_i2c2_gpio: i2c2-gpiogrp {
736 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>,
737 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>;
741 fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x400001e2>,
742 <MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x400001e2>;
745 pinctrl_i2c3_gpio: i2c3-gpiogrp {
746 fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400001e2>,
747 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x400001e2>;
751 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001e2>,
752 <MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001e2>;
755 pinctrl_i2c4_gpio: i2c4-gpiogrp {
756 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x400001e2>,
757 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x400001e2>;
761 fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e2>,
762 <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e2>;
765 pinctrl_i2c5_gpio: i2c5-gpiogrp {
766 fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001e2>,
767 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001e2>;
771 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>,
772 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>;
775 pinctrl_i2c6_gpio: i2c6-gpiogrp {
776 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>,
777 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>;
781 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x80>;
785 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>,
786 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x94>;
790 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10>;
794 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x14>;
798 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x14>;
802 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>;
806 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x14>;
810 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>;
814 fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x14>;
818 fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x94>,
819 <MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94>,
820 <MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x94>,
821 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x94>,
822 <MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x94>;
826 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x180>;
830 fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>,
831 <MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>,
832 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>,
833 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>;
837 fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x80>,
838 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x80>,
839 <MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x80>,
840 <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x80>;
844 fsl,pins = <MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x14>,
845 <MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x14>,
846 <MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x14>,
847 <MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x14>;
851 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>,
852 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>;
856 fsl,pins = <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>,
857 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>;
861 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>;
865 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x192>,
866 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d2>,
867 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d2>,
868 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d2>,
869 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d2>,
870 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d2>;
874 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>,
875 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>,
876 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
877 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
878 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
879 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
880 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
883 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
884 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
885 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
886 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
887 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
888 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
889 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
890 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
893 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
894 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
895 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
896 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
897 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
898 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
899 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
900 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
903 pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
904 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>;