Lines Matching +full:0 +full:x28000000
15 reg = <0x00000000 0x40000000 0 0x40000000>;
43 size = <0 0x28000000>;
45 alloc-ranges = <0 0x40000000 0 0x78000000>;
57 pinctrl-0 = <&pinctrl_flexspi>;
60 flash0: flash@0 {
62 reg = <0>;
78 pinctrl-0 = <&pinctrl_i2c1>;
86 reg = <0x1b>;
91 reg = <0x25>;
94 pinctrl-0 = <&pinctrl_pmic>;
206 reg = <0x51>;
213 reg = <0x53>;
220 reg = <0x57>;
233 pinctrl-0 = <&pinctrl_usdhc3>;
252 pinctrl-0 = <&pinctrl_wdog>;
259 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>,
260 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>,
261 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>,
262 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>,
263 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>,
264 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>;
268 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>,
269 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>;
273 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>,
274 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>;
278 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
282 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
286 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
287 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
288 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
289 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
290 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
291 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
292 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
293 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
294 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
295 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
296 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
297 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
301 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
302 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
303 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
304 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
305 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
306 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
307 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
308 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
309 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
310 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
311 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
312 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
316 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
317 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
318 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
319 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
320 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
321 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
322 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
323 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
324 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
325 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
326 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
327 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
331 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;