Lines Matching +full:0 +full:x90
21 reg = <0x0 0x40000000 0 0x80000000>;
76 pinctrl-0 = <&pinctrl_fec1>;
81 #size-cells = <0>;
83 ethphy0: ethernet-phy@0 {
90 reg = <0>;
101 pinctrl-0 = <&pinctrl_flexspi0>;
104 som_flash: flash@0 {
108 reg = <0>;
125 pinctrl-0 = <&pinctrl_i2c1>;
133 reg = <0x08>;
286 pinctrl-0 = <&pinctrl_sn65dsi83>;
287 reg = <0x2d>;
294 reg = <0x51>;
303 pinctrl-0 = <&pinctrl_rtc>;
304 reg = <0x52>;
315 pinctrl-0 = <&pinctrl_usdhc3>;
326 pinctrl-0 = <&pinctrl_wdog>;
333 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2
334 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2
335 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
336 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
337 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
338 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
339 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
340 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
341 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
342 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
343 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
344 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
345 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
346 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
347 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
353 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
354 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
355 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
356 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
357 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
358 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
364 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0
365 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0
371 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0
372 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0
378 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
384 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0
390 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
391 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
392 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
393 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
394 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
395 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
396 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
397 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
398 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
399 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
400 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
406 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
407 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
408 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
409 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
410 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
411 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
412 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
413 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
414 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
415 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
416 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
422 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
423 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
424 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
425 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
426 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
427 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
428 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
429 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
430 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
431 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
432 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
438 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26