dts/freescale/imx8dxl.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
14 #include <dt-bindings/thermal/thermal.h>
17 	interrupt-parent = <&gic>;
18 	#address-cells = <2>;
19 	#size-cells = <2>;
36 		#address-cells = <2>;
37 		#size-cells = <0>;
39 		/* We have 1 clusters with 2 Cortex-A35 cores */
42 			compatible = "arm,cortex-a35";
44 			enable-method = "psci";
45 			next-level-cache = <&A35_L2>;
47 			#cooling-cells = <2>;
48 			operating-points-v2 = <&a35_opp_table>;
53 			compatible = "arm,cortex-a35";
55 			enable-method = "psci";
56 			next-level-cache = <&A35_L2>;
58 			#cooling-cells = <2>;
59 			operating-points-v2 = <&a35_opp_table>;
62 		A35_L2: l2-cache0 {
64 			cache-level = <2>;
65 			cache-unified;
69 	a35_opp_table: opp-table {
70 		compatible = "operating-points-v2";
71 		opp-shared;
73 		opp-900000000 {
74 			opp-hz = /bits/ 64 <900000000>;
75 			opp-microvolt = <1000000>;
76 			clock-latency-ns = <150000>;
79 		opp-1200000000 {
80 			opp-hz = /bits/ 64 <1200000000>;
81 			opp-microvolt = <1100000>;
82 			clock-latency-ns = <150000>;
83 			opp-suspend;
87 	gic: interrupt-controller@51a00000 {
88 		compatible = "arm,gic-v3";
91 		#interrupt-cells = <3>;
92 		interrupt-controller;
96 	reserved-memory {
97 		#address-cells = <2>;
98 		#size-cells = <2>;
103 			no-map;
108 		compatible = "arm,cortex-a35-pmu";
113 		compatible = "arm,psci-1.0";
117 	system-controller {
118 		compatible = "fsl,imx-scu";
119 		mbox-names = "tx0",
126 		pd: power-controller {
127 			compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd";
128 			#power-domain-cells = <1>;
131 		clk: clock-controller {
132 			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
133 			#clock-cells = <2>;
137 			compatible = "fsl,imx8qxp-sc-gpio";
138 			gpio-controller;
139 			#gpio-cells = <2>;
143 			compatible = "fsl,imx8dxl-iomuxc";
147 			compatible = "fsl,imx8qxp-scu-ocotp";
148 			#address-cells = <1>;
149 			#size-cells = <1>;
161 			compatible = "fsl,imx8qxp-sc-rtc";
165 			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
167 			wakeup-source;
171 			compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt";
172 			timeout-sec = <60>;
175 		tsens: thermal-sensor {
176 			compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal";
177 			#thermal-sensor-cells = <1>;
181 	timer {
182 		compatible = "arm,armv8-timer";
183 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
184 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
189 	thermal_zones: thermal-zones {
190 		cpu-thermal {
191 			polling-delay-passive = <250>;
192 			polling-delay = <2000>;
193 			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
208 			cooling-maps {
211 					cooling-device =
220 	xtal32k: clock-xtal32k {
221 		compatible = "fixed-clock";
222 		#clock-cells = <0>;
223 		clock-frequency = <32768>;
224 		clock-output-names = "xtal_32KHz";
227 	xtal24m: clock-xtal24m {
228 		compatible = "fixed-clock";
229 		#clock-cells = <0>;
230 		clock-frequency = <24000000>;
231 		clock-output-names = "xtal_24MHz";
235 	#include "imx8-ss-cm40.dtsi"
236 	#include "imx8-ss-adma.dtsi"
237 	#include "imx8-ss-conn.dtsi"
238 	#include "imx8-ss-ddr.dtsi"
239 	#include "imx8-ss-lsio.dtsi"
242 #include "imx8dxl-ss-adma.dtsi"
243 #include "imx8dxl-ss-conn.dtsi"
244 #include "imx8dxl-ss-lsio.dtsi"
245 #include "imx8dxl-ss-ddr.dtsi"