Lines Matching +full:clock +full:- +full:indices
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
24 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
26 assigned-clock-rates = <200000000>, <200000000>;
27 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
36 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
38 assigned-clock-rates = <200000000>, <200000000>;
39 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
43 img_jpeg_dec_lpcg: clock-controller@585d0000 {
44 compatible = "fsl,imx8qxp-lpcg";
46 #clock-cells = <1>;
48 clock-indices = <IMX_LPCG_CLK_0>,
50 clock-output-names = "img_jpeg_dec_lpcg_clk",
52 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
55 img_jpeg_enc_lpcg: clock-controller@585f0000 {
56 compatible = "fsl,imx8qxp-lpcg";
58 #clock-cells = <1>;
60 clock-indices = <IMX_LPCG_CLK_0>,
62 clock-output-names = "img_jpeg_enc_lpcg_clk",
64 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;