Lines Matching +full:0 +full:x5a880000
13 #clock-cells = <0>;
22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
26 reg = <0x5a000000 0x10000>;
28 #size-cells = <0>;
37 dmas = <&edma2 1 0 0>, <&edma2 0 0 FSL_EDMA_RX>;
44 reg = <0x5a010000 0x10000>;
46 #size-cells = <0>;
55 dmas = <&edma2 3 0 0>, <&edma2 2 0 FSL_EDMA_RX>;
62 reg = <0x5a020000 0x10000>;
64 #size-cells = <0>;
73 dmas = <&edma2 5 0 0>, <&edma2 4 0 FSL_EDMA_RX>;
80 reg = <0x5a030000 0x10000>;
82 #size-cells = <0>;
91 dmas = <&edma2 7 0 0>, <&edma2 6 0 FSL_EDMA_RX>;
97 reg = <0x5a060000 0x1000>;
106 dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>;
111 reg = <0x5a070000 0x1000>;
120 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>;
125 reg = <0x5a080000 0x1000>;
134 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
139 reg = <0x5a090000 0x1000>;
148 dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
154 reg = <0x5a190000 0x1000>;
167 reg = <0x5a1f0000 0x170000>;
206 reg = <0x5a400000 0x10000>;
218 reg = <0x5a410000 0x10000>;
230 reg = <0x5a420000 0x10000>;
242 reg = <0x5a430000 0x10000>;
254 reg = <0x5a460000 0x10000>;
266 reg = <0x5a470000 0x10000>;
278 reg = <0x5a480000 0x10000>;
290 reg = <0x5a490000 0x10000>;
302 reg = <0x5a590000 0x10000>;
313 reg = <0x5a800000 0x4000>;
315 #size-cells = <0>;
327 reg = <0x5a810000 0x4000>;
329 #size-cells = <0>;
341 reg = <0x5a820000 0x4000>;
343 #size-cells = <0>;
355 reg = <0x5a830000 0x4000>;
357 #size-cells = <0>;
371 reg = <0x5a880000 0x10000>;
386 reg = <0x5a890000 0x10000>;
400 reg = <0x5a8d0000 0x10000>;
410 fsl,clk-source = /bits/ 8 <0>;
411 fsl,scu-index = /bits/ 8 <0>;
417 reg = <0x5a8e0000 0x10000>;
431 fsl,clk-source = /bits/ 8 <0>;
438 reg = <0x5a8f0000 0x10000>;
452 fsl,clk-source = /bits/ 8 <0>;
459 reg = <0x5a9f0000 0x90000>;
482 reg = <0x5ac00000 0x10000>;
494 reg = <0x5ac10000 0x10000>;
506 reg = <0x5ac20000 0x10000>;
518 reg = <0x5ac30000 0x10000>;
530 reg = <0x5ac80000 0x10000>;
542 reg = <0x5ac90000 0x10000>;
554 reg = <0x5acd0000 0x10000>;