Lines Matching +full:imx8qxp +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
9 cm40_ipg_clk: clock-cm40-ipg {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <132000000>;
13 clock-output-names = "cm40_ipg_clk";
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
21 interrupt-parent = <&cm40_intmux>;
24 compatible = "fsl,imx8qxp-lpuart";
28 clock-names = "ipg", "baud";
29 assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
30 assigned-clock-rates = <24000000>;
31 power-domains = <&pd IMX_SC_R_M4_0_UART>;
36 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
41 clock-names = "per", "ipg";
42 assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
43 assigned-clock-rates = <24000000>;
44 power-domains = <&pd IMX_SC_R_M4_0_I2C>;
49 compatible = "fsl,imx-intmux";
51 interrupt-parent = <&gic>;
60 interrupt-controller;
61 #interrupt-cells = <2>;
63 clock-names = "ipg";
64 power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
68 cm40_uart_lpcg: clock-controller@37620000 {
69 compatible = "fsl,imx8qxp-lpcg";
71 #clock-cells = <1>;
74 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
75 clock-output-names = "cm40_lpcg_uart_clk",
77 power-domains = <&pd IMX_SC_R_M4_0_UART>;
80 cm40_i2c_lpcg: clock-controller@37630000 {
81 compatible = "fsl,imx8qxp-lpcg";
83 #clock-cells = <1>;
86 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
87 clock-output-names = "cm40_lpcg_i2c_clk",
89 power-domains = <&pd IMX_SC_R_M4_0_I2C>;