Lines Matching +full:4 +full:e80000
244 sfp: efuse@1e80000 {
248 QORIQ_CLK_PLL_DIV(4)>;
278 QORIQ_CLK_PLL_DIV(4)>;
289 QORIQ_CLK_PLL_DIV(4)>;
300 QORIQ_CLK_PLL_DIV(4)>;
311 QORIQ_CLK_PLL_DIV(4)>;
322 QORIQ_CLK_PLL_DIV(4)>;
333 QORIQ_CLK_PLL_DIV(4)>;
344 QORIQ_CLK_PLL_DIV(4)>;
355 QORIQ_CLK_PLL_DIV(4)>;
383 spi-num-chipselects = <4>;
398 spi-num-chipselects = <4>;
426 bus-width = <4>;
440 bus-width = <4>;
621 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
631 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
668 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
707 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
905 <&edma0 1 4>;
1137 ethernet@0,4 {
1177 mscc_felix_port4: port@4 {
1178 reg = <4>;
1237 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1238 <&rtc_clk>, <&clockgen 4 1>;
1248 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1249 <&rtc_clk>, <&clockgen 4 1>;
1259 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1260 <&rtc_clk>, <&clockgen 4 1>;
1270 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1271 <&rtc_clk>, <&clockgen 4 1>;
1281 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1282 <&rtc_clk>, <&clockgen 4 1>;
1292 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1293 <&rtc_clk>, <&clockgen 4 1>;
1303 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1304 <&rtc_clk>, <&clockgen 4 1>;
1314 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1315 <&rtc_clk>, <&clockgen 4 1>;