Lines Matching full:cmu_top
369 cmu_top: clock-controller@10030000 { label
433 <&cmu_top CLK_ACLK_FSYS_200>,
434 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
435 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
436 <&cmu_top CLK_SCLK_MMC2_FSYS>,
437 <&cmu_top CLK_SCLK_MMC1_FSYS>,
438 <&cmu_top CLK_SCLK_MMC0_FSYS>,
439 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
440 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
452 <&cmu_top CLK_ACLK_G2D_266>,
453 <&cmu_top CLK_ACLK_G2D_400>;
488 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
498 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
507 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
525 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
538 <&cmu_top CLK_ACLK_GSCL_111>,
539 <&cmu_top CLK_ACLK_GSCL_333>;
570 <&cmu_top CLK_SCLK_JPEG_MSCL>,
571 <&cmu_top CLK_ACLK_MSCL_400>;
581 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
591 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
604 <&cmu_top CLK_ACLK_ISP_DIS_400>,
605 <&cmu_top CLK_ACLK_ISP_400>;
619 <&cmu_top CLK_ACLK_CAM0_333>,
620 <&cmu_top CLK_ACLK_CAM0_400>,
621 <&cmu_top CLK_ACLK_CAM0_552>;
638 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
639 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
640 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
641 <&cmu_top CLK_ACLK_CAM1_333>,
642 <&cmu_top CLK_ACLK_CAM1_400>,
643 <&cmu_top CLK_ACLK_CAM1_552>;
657 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
658 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
659 <&cmu_top CLK_DIV_ACLK_IMEM_200>;