Lines Matching full:cmu_fsys
416 cmu_fsys: clock-controller@156e0000 { label
1765 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1766 <&cmu_fsys CLK_SCLK_USBDRD30>,
1767 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1768 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1777 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1778 <&cmu_fsys CLK_ACLK_USBDRD30>,
1779 <&cmu_fsys CLK_SCLK_USBDRD30>;
1791 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1792 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1793 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1794 <&cmu_fsys CLK_SCLK_USBDRD30>;
1805 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1806 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1807 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1808 <&cmu_fsys CLK_SCLK_USBHOST30>;
1818 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1819 <&cmu_fsys CLK_SCLK_USBHOST30>,
1820 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1821 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1830 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1831 <&cmu_fsys CLK_ACLK_USBHOST30>,
1832 <&cmu_fsys CLK_SCLK_USBHOST30>;
1848 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1849 <&cmu_fsys CLK_SCLK_MMC0>;
1862 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1863 <&cmu_fsys CLK_SCLK_MMC1>;
1876 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1877 <&cmu_fsys CLK_SCLK_MMC2>;
1887 clocks = <&cmu_fsys CLK_PDMA0>;
1896 clocks = <&cmu_fsys CLK_PDMA1>;
1975 clocks = <&cmu_fsys CLK_PCIE>,
1976 <&cmu_fsys CLK_PCLK_PCIE_PHY>;