Lines Matching full:cmu_top
228 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>;
246 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
249 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>;
262 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
287 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK_ACLK_GSCL_333>;
293 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
306 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK_SCLK_JPEG_MSCL>,
310 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
313 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
969 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
995 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
996 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
997 <&cmu_top CLK_MOUT_BUS_PLL_USER>;