Lines Matching +full:gic +full:- +full:400
35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
58 compatible = "arm,cortex-a57";
60 enable-method = "psci";
61 next-level-cache = <&CLUSTER0_L2>;
66 compatible = "arm,cortex-a57";
68 enable-method = "psci";
69 next-level-cache = <&CLUSTER0_L2>;
74 compatible = "arm,cortex-a57";
76 enable-method = "psci";
77 next-level-cache = <&CLUSTER0_L2>;
80 CLUSTER0_L2: l2-cache@0 {
82 cache-level = <2>;
83 cache-unified;
88 compatible = "arm,psci-1.0";
93 compatible = "arm,armv8-timer";
105 compatible = "arm,cortex-a57-pmu";
110 interrupt-affinity = <&A57_0>,
117 compatible = "brcm,iproc-pcie";
119 dma-coherent;
121 #interrupt-cells = <1>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
125 linux,pci-domain = <0>;
127 bus-range = <0x00 0xff>;
129 #address-cells = <3>;
130 #size-cells = <2>;
134 brcm,pcie-ob;
135 brcm,pcie-ob-oarr-size;
136 brcm,pcie-ob-axi-offset = <0x00000000>;
137 brcm,pcie-ob-window-size = <256>;
142 phy-names = "pcie-phy";
144 msi-parent = <&v2m0>;
148 compatible = "brcm,iproc-pcie";
150 dma-coherent;
152 #interrupt-cells = <1>;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
156 linux,pci-domain = <4>;
158 bus-range = <0x00 0xff>;
160 #address-cells = <3>;
161 #size-cells = <2>;
165 brcm,pcie-ob;
166 brcm,pcie-ob-oarr-size;
167 brcm,pcie-ob-axi-offset = <0x30000000>;
168 brcm,pcie-ob-window-size = <256>;
173 phy-names = "pcie-phy";
175 msi-parent = <&v2m0>;
179 compatible = "brcm,iproc-pcie-paxc";
181 dma-coherent;
182 linux,pci-domain = <8>;
184 bus-range = <0x0 0x1>;
186 #address-cells = <3>;
187 #size-cells = <2>;
193 msi-parent = <&v2m0>;
197 compatible = "simple-bus";
198 #address-cells = <1>;
199 #size-cells = <1>;
202 #include "ns2-clock.dtsi"
205 compatible = "brcm,ns2-amac";
209 reg-names = "amac_base", "idm_base", "nicpm_base";
211 dma-coherent;
212 phy-handle = <&gphy0>;
213 phy-mode = "rgmii";
217 pdc0: iproc-pdc0@612c0000 {
218 compatible = "brcm,iproc-pdc-mbox";
221 #mbox-cells = <1>;
222 dma-coherent;
223 brcm,rx-status-len = <32>;
224 brcm,use-bcm-hdr;
228 compatible = "brcm,spum-crypto";
233 pdc1: iproc-pdc1@612e0000 {
234 compatible = "brcm,iproc-pdc-mbox";
237 #mbox-cells = <1>;
238 dma-coherent;
239 brcm,rx-status-len = <32>;
240 brcm,use-bcm-hdr;
244 compatible = "brcm,spum-crypto";
249 pdc2: iproc-pdc2@61300000 {
250 compatible = "brcm,iproc-pdc-mbox";
253 #mbox-cells = <1>;
254 dma-coherent;
255 brcm,rx-status-len = <32>;
256 brcm,use-bcm-hdr;
260 compatible = "brcm,spum-crypto";
265 pdc3: iproc-pdc3@61320000 {
266 compatible = "brcm,iproc-pdc-mbox";
269 #mbox-cells = <1>;
270 dma-coherent;
271 brcm,rx-status-len = <32>;
272 brcm,use-bcm-hdr;
276 compatible = "brcm,spum-crypto";
281 dma0: dma-controller@61360000 {
293 #dma-cells = <1>;
295 clock-names = "apb_pclk";
299 compatible = "arm,mmu-500";
301 #global-interrupts = <2>;
336 #iommu-cells = <1>;
340 compatible = "brcm,ns2-pinmux";
347 compatible = "brcm,iproc-gpio";
351 #gpio-cells = <2>;
352 gpio-controller;
355 gic: interrupt-controller@65210000 { label
356 compatible = "arm,gic-400";
357 #interrupt-cells = <3>;
358 interrupt-controller;
366 #address-cells = <1>;
367 #size-cells = <1>;
371 compatible = "arm,gic-v2m-frame";
372 interrupt-parent = <&gic>;
373 msi-controller;
375 arm,msi-base-spi = <72>;
376 arm,msi-num-spis = <16>;
380 compatible = "arm,gic-v2m-frame";
381 interrupt-parent = <&gic>;
382 msi-controller;
384 arm,msi-base-spi = <88>;
385 arm,msi-num-spis = <16>;
389 compatible = "arm,gic-v2m-frame";
390 interrupt-parent = <&gic>;
391 msi-controller;
393 arm,msi-base-spi = <104>;
394 arm,msi-num-spis = <16>;
398 compatible = "arm,gic-v2m-frame";
399 interrupt-parent = <&gic>;
400 msi-controller;
402 arm,msi-base-spi = <120>;
403 arm,msi-num-spis = <16>;
407 compatible = "arm,gic-v2m-frame";
408 interrupt-parent = <&gic>;
409 msi-controller;
411 arm,msi-base-spi = <136>;
412 arm,msi-num-spis = <16>;
416 compatible = "arm,gic-v2m-frame";
417 interrupt-parent = <&gic>;
418 msi-controller;
420 arm,msi-base-spi = <152>;
421 arm,msi-num-spis = <16>;
425 compatible = "arm,gic-v2m-frame";
426 interrupt-parent = <&gic>;
427 msi-controller;
429 arm,msi-base-spi = <168>;
430 arm,msi-num-spis = <16>;
434 compatible = "arm,gic-v2m-frame";
435 interrupt-parent = <&gic>;
436 msi-controller;
438 arm,msi-base-spi = <184>;
439 arm,msi-num-spis = <16>;
444 compatible = "arm,cci-400";
445 #address-cells = <1>;
446 #size-cells = <1>;
451 compatible = "arm,cci-400-pmu,r1",
452 "arm,cci-400-pmu";
464 #phy-cells = <0>;
465 compatible = "brcm,ns2-drd-phy";
470 reg-names = "icfg", "rst-ctrl",
471 "crmu-ctrl", "usb2-strap";
472 id-gpios = <&gpio_g 30 0>;
473 vbus-gpios = <&gpio_g 31 0>;
478 compatible = "brcm,iproc-pwm";
481 #pwm-cells = <3>;
485 mdio_mux_iproc: mdio-mux@66020000 {
486 compatible = "brcm,mdio-mux-iproc";
488 #address-cells = <1>;
489 #size-cells = <0>;
493 #address-cells = <1>;
494 #size-cells = <0>;
496 pci_phy0: pci-phy@0 {
497 compatible = "brcm,ns2-pcie-phy";
499 #phy-cells = <0>;
506 #address-cells = <1>;
507 #size-cells = <0>;
509 pci_phy1: pci-phy@0 {
510 compatible = "brcm,ns2-pcie-phy";
512 #phy-cells = <0>;
519 #address-cells = <1>;
520 #size-cells = <0>;
531 clock-names = "timer1", "timer2", "apb_pclk";
541 clock-names = "timer1", "timer2", "apb_pclk";
551 clock-names = "timer1", "timer2", "apb_pclk";
561 clock-names = "timer1", "timer2", "apb_pclk";
565 compatible = "brcm,iproc-i2c";
567 #address-cells = <1>;
568 #size-cells = <0>;
570 clock-frequency = <100000>;
579 clock-names = "wdog_clk", "apb_pclk";
583 compatible = "brcm,iproc-gpio";
586 #gpio-cells = <2>;
587 gpio-controller;
588 interrupt-controller;
589 #interrupt-cells = <2>;
590 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
594 compatible = "brcm,iproc-i2c";
596 #address-cells = <1>;
597 #size-cells = <0>;
599 clock-frequency = <100000>;
604 compatible = "snps,dw-apb-uart";
608 reg-shift = <2>;
609 reg-io-width = <4>;
614 compatible = "snps,dw-apb-uart";
618 reg-shift = <2>;
619 reg-io-width = <4>;
624 compatible = "snps,dw-apb-uart";
628 reg-shift = <2>;
629 reg-io-width = <4>;
634 compatible = "snps,dw-apb-uart";
637 reg-shift = <2>;
638 reg-io-width = <4>;
648 clock-names = "sspclk", "apb_pclk";
649 #address-cells = <1>;
650 #size-cells = <0>;
659 clock-names = "sspclk", "apb_pclk";
660 #address-cells = <1>;
661 #size-cells = <0>;
666 compatible = "brcm,iproc-rng200";
671 compatible = "brcm,iproc-ns2-sata-phy";
674 reg-names = "phy", "phy-ctrl";
675 #address-cells = <1>;
676 #size-cells = <0>;
678 sata_phy0: sata-phy@0 {
680 #phy-cells = <0>;
684 sata_phy1: sata-phy@1 {
686 #phy-cells = <0>;
692 compatible = "brcm,iproc-ahci", "generic-ahci";
694 dma-coherent;
695 reg-names = "ahci";
697 #address-cells = <1>;
698 #size-cells = <0>;
701 sata0: sata-port@0 {
704 phy-names = "sata-phy";
707 sata1: sata-port@1 {
710 phy-names = "sata-phy";
715 compatible = "brcm,sdhci-iproc-cygnus";
718 dma-coherent;
719 bus-width = <8>;
725 compatible = "brcm,sdhci-iproc-cygnus";
728 dma-coherent;
729 bus-width = <8>;
735 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
739 reg-names = "nand", "iproc-idm", "iproc-ext";
742 #address-cells = <1>;
743 #size-cells = <0>;
745 brcm,nand-has-wp;
749 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
754 reg-names = "mspi", "bspi", "intr_regs",
757 interrupt-names = "spi_l1_intr";
759 clock-names = "iprocmed";
760 num-cs = <2>;
761 #address-cells = <1>;
762 #size-cells = <0>;