Lines Matching +full:0 +full:x20020000
33 /memreserve/ 0x81000000 0x00200000;
46 #size-cells = <0>;
48 A57_0: cpu@0 {
51 reg = <0 0>;
59 reg = <0 1>;
67 reg = <0 2>;
75 reg = <0 3>;
80 CLUSTER0_L2: l2-cache@0 {
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
98 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
100 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
118 reg = <0 0x20020000 0 0x1000>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
125 linux,pci-domain = <0>;
127 bus-range = <0x00 0xff>;
132 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
136 brcm,pcie-ob-axi-offset = <0x00000000>;
149 reg = <0 0x50020000 0 0x1000>;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
158 bus-range = <0x00 0xff>;
163 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
167 brcm,pcie-ob-axi-offset = <0x30000000>;
180 reg = <0 0x60c00000 0 0x1000>;
184 bus-range = <0x0 0x1>;
189 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>;
200 ranges = <0 0 0 0xffffffff>;
206 reg = <0x61000000 0x1000>,
207 <0x61090000 0x1000>,
208 <0x61030000 0x100>;
219 reg = <0x612c0000 0x445>; /* PDC FS0 regs */
229 reg = <0x612d0000 0x900>;
230 mboxes = <&pdc0 0>;
235 reg = <0x612e0000 0x445>; /* PDC FS1 regs */
245 reg = <0x612f0000 0x900>;
246 mboxes = <&pdc1 0>;
251 reg = <0x61300000 0x445>; /* PDC FS2 regs */
261 reg = <0x61310000 0x900>;
262 mboxes = <&pdc2 0>;
267 reg = <0x61320000 0x445>; /* PDC FS3 regs */
277 reg = <0x61330000 0x900>;
278 mboxes = <&pdc3 0>;
283 reg = <0x61360000 0x1000>;
300 reg = <0x64000000 0x40000>;
341 reg = <0x6501d130 0x08>,
342 <0x660a0028 0x04>,
343 <0x660009b0 0x40>;
348 reg = <0x65024800 0x50>,
349 <0x65024008 0x18>;
359 reg = <0x65210000 0x1000>,
360 <0x65220000 0x1000>,
361 <0x65240000 0x2000>,
362 <0x65260000 0x1000>;
363 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
368 ranges = <0 0x652e0000 0x80000>;
370 v2m0: v2m@0 {
374 reg = <0x00000 0x1000>;
383 reg = <0x10000 0x1000>;
392 reg = <0x20000 0x1000>;
401 reg = <0x30000 0x1000>;
410 reg = <0x40000 0x1000>;
419 reg = <0x50000 0x1000>;
428 reg = <0x60000 0x1000>;
437 reg = <0x70000 0x1000>;
447 reg = <0x65590000 0x1000>;
448 ranges = <0 0x65590000 0x10000>;
453 reg = <0x9000 0x4000>;
464 #phy-cells = <0>;
466 reg = <0x66000960 0x24>,
467 <0x67012800 0x4>,
468 <0x6501d148 0x4>,
469 <0x664d0700 0x4>;
472 id-gpios = <&gpio_g 30 0>;
473 vbus-gpios = <&gpio_g 31 0>;
479 reg = <0x66010000 0x28>;
487 reg = <0x66020000 0x250>;
489 #size-cells = <0>;
491 mdio@0 {
492 reg = <0x0>;
494 #size-cells = <0>;
496 pci_phy0: pci-phy@0 {
498 reg = <0x0>;
499 #phy-cells = <0>;
505 reg = <0x7>;
507 #size-cells = <0>;
509 pci_phy1: pci-phy@0 {
511 reg = <0x0>;
512 #phy-cells = <0>;
518 reg = <0x10>;
520 #size-cells = <0>;
526 reg = <0x66030000 0x1000>;
536 reg = <0x66040000 0x1000>;
546 reg = <0x66050000 0x1000>;
556 reg = <0x66060000 0x1000>;
566 reg = <0x66080000 0x100>;
568 #size-cells = <0>;
576 reg = <0x66090000 0x1000>;
584 reg = <0x660a0000 0x50>;
595 reg = <0x660b0000 0x100>;
597 #size-cells = <0>;
605 reg = <0x66100000 0x100>;
615 reg = <0x66110000 0x100>;
625 reg = <0x66120000 0x100>;
635 reg = <0x66130000 0x100>;
645 reg = <0x66180000 0x1000>;
650 #size-cells = <0>;
656 reg = <0x66190000 0x1000>;
661 #size-cells = <0>;
667 reg = <0x66220000 0x28>;
672 reg = <0x663f0100 0x1f00>,
673 <0x663f004c 0x10>;
676 #size-cells = <0>;
678 sata_phy0: sata-phy@0 {
679 reg = <0>;
680 #phy-cells = <0>;
686 #phy-cells = <0>;
693 reg = <0x663f2000 0x1000>;
698 #size-cells = <0>;
701 sata0: sata-port@0 {
702 reg = <0>;
716 reg = <0x66420000 0x100>;
726 reg = <0x66430000 0x100>;
736 reg = <0x66460000 0x600>,
737 <0x67015408 0x600>,
738 <0x66460f00 0x20>;
743 #size-cells = <0>;
750 reg = <0x66470200 0x184>,
751 <0x66470000 0x124>,
752 <0x67017408 0x004>,
753 <0x664703a0 0x01c>;
762 #size-cells = <0>;