broadcom/bcmbca/bcm63146.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 	#address-cells = <2>;
12 	#size-cells = <2>;
14 	interrupt-parent = <&gic>;
17 		#address-cells = <2>;
18 		#size-cells = <0>;
21 			compatible = "brcm,brahma-b53";
24 			next-level-cache = <&L2_0>;
25 			enable-method = "psci";
29 			compatible = "brcm,brahma-b53";
32 			next-level-cache = <&L2_0>;
33 			enable-method = "psci";
36 		L2_0: l2-cache0 {
38 			cache-level = <2>;
39 			cache-unified;
44 		compatible = "arm,armv8-timer";
52 		compatible = "arm,cortex-a53-pmu";
55 		interrupt-affinity = <&B53_0>, <&B53_1>;
59 		periph_clk: periph-clk {
60 			compatible = "fixed-clock";
61 			#clock-cells = <0>;
62 			clock-frequency = <200000000>;
65 		uart_clk: uart-clk {
66 			compatible = "fixed-factor-clock";
67 			#clock-cells = <0>;
69 			clock-div = <4>;
70 			clock-mult = <1>;
73 		hsspi_pll: hsspi-pll {
74 			compatible = "fixed-clock";
75 			#clock-cells = <0>;
76 			clock-frequency = <200000000>;
81 		compatible = "arm,psci-0.2";
86 		compatible = "simple-bus";
87 		#address-cells = <1>;
88 		#size-cells = <1>;
91 		gic: interrupt-controller@1000 {  label
92 			compatible = "arm,gic-400";
93 			#interrupt-cells = <3>;
94 			interrupt-controller;
105 		compatible = "simple-bus";
106 		#address-cells = <1>;
107 		#size-cells = <1>;
111 			#address-cells = <1>;
112 			#size-cells = <0>;
113 			compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
117 			clock-names = "hsspi", "pll";
118 			num-cs = <8>;
122 		nand_controller: nand-controller@1800 {
123 			#address-cells = <1>;
124 			#size-cells = <0>;
125 			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
127 			reg-names = "nand", "nand-int-base";
141 			clock-names = "uartclk", "apb_pclk";