Lines Matching +full:0 +full:x80000
16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x000>;
59 d-cache-size = <0x10000>;
62 i-cache-size = <0x10000>;
69 cache-size = <0x80000>;
81 reg = <0x100>;
83 d-cache-size = <0x10000>;
86 i-cache-size = <0x10000>;
93 cache-size = <0x80000>;
105 reg = <0x200>;
107 d-cache-size = <0x10000>;
110 i-cache-size = <0x10000>;
117 cache-size = <0x80000>;
129 reg = <0x300>;
131 d-cache-size = <0x10000>;
134 i-cache-size = <0x10000>;
141 cache-size = <0x80000>;
157 cache-size = <0x200000>;
175 atf@0 {
176 reg = <0x0 0x0 0x0 0x80000>;
182 size = <0x0 0x4000000>; /* 64MB */
185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
191 ranges = <0x00000000 0x10 0x00000000 0x80000000>;
198 reg = <0x00fff000 0x260>,
199 <0x00fff400 0x200>;
209 reg = <0x7c003000 0x1000>;
219 reg = <0x7c013880 0x40>;
221 #mbox-cells = <0>;
226 reg = <0x7cd00000 0x100>;
231 reg = <0x7d001000 0x200>;
235 arm,primecell-periphid = <0x00241011>;
241 reg = <0x7d517000 0x10>;
249 reg = <0x7d517c00 0x40>;
261 reg = <0x7fff9000 0x1000>,
262 <0x7fffa000 0x2000>,
263 <0x7fffc000 0x2000>,
264 <0x7fffe000 0x2000>;