dts/arm/rtsm_ve-aemv8a.dts

1 // SPDX-License-Identifier: GPL-2.0
5  * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 	interrupt-parent = <&gic>;
23 	#address-cells = <2>;
24 	#size-cells = <2>;
27 		stdout-path = "serial0:115200n8";
38 		#address-cells = <2>;
39 		#size-cells = <0>;
45 			enable-method = "spin-table";
46 			cpu-release-addr = <0x0 0x8000fff8>;
47 			next-level-cache = <&L2_0>;
53 			enable-method = "spin-table";
54 			cpu-release-addr = <0x0 0x8000fff8>;
55 			next-level-cache = <&L2_0>;
61 			enable-method = "spin-table";
62 			cpu-release-addr = <0x0 0x8000fff8>;
63 			next-level-cache = <&L2_0>;
69 			enable-method = "spin-table";
70 			cpu-release-addr = <0x0 0x8000fff8>;
71 			next-level-cache = <&L2_0>;
74 		L2_0: l2-cache0 {
76 			cache-level = <2>;
77 			cache-unified;
87 	reserved-memory {
88 		#address-cells = <2>;
89 		#size-cells = <2>;
95 			compatible = "shared-dma-pool";
97 			no-map;
101 	gic: interrupt-controller@2c001000 {
102 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
103 		#interrupt-cells = <3>;
104 		#address-cells = <0>;
105 		interrupt-controller;
114 		compatible = "arm,armv8-timer";
119 		clock-frequency = <100000000>;
123 		compatible = "arm,armv8-pmuv3";
131 		compatible = "arm,rtsm-display";
134 				remote-endpoint = <&clcd_pads>;
140 		#interrupt-cells = <1>;
141 		interrupt-map-mask = <0 0 63>;
142 		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,