Lines Matching +full:0 +full:x2c010000
15 /memreserve/ 0x80000000 0x00010000;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x000>;
52 i-cache-size = <0x8000>;
55 d-cache-size = <0x8000>;
63 reg = <0x0 0x100>;
65 i-cache-size = <0x8000>;
68 d-cache-size = <0x8000>;
76 reg = <0x0 0x200>;
78 i-cache-size = <0x8000>;
81 d-cache-size = <0x8000>;
89 reg = <0x0 0x300>;
91 i-cache-size = <0x8000>;
94 d-cache-size = <0x8000>;
102 reg = <0x0 0x10000>;
104 i-cache-size = <0x8000>;
107 d-cache-size = <0x8000>;
115 reg = <0x0 0x10100>;
117 i-cache-size = <0x8000>;
120 d-cache-size = <0x8000>;
128 reg = <0x0 0x10200>;
130 i-cache-size = <0x8000>;
133 d-cache-size = <0x8000>;
141 reg = <0x0 0x10300>;
143 i-cache-size = <0x8000>;
146 d-cache-size = <0x8000>;
153 cache-size = <0x80000>;
162 cache-size = <0x80000>;
172 reg = <0x00000000 0x80000000 0 0x80000000>,
173 <0x00000008 0x80000000 0 0x80000000>;
181 /* Chipselect 2,00000000 is physically at 0x18000000 */
185 reg = <0x00000000 0x18000000 0 0x00800000>;
197 reg = <0x0 0x2f000000 0 0x10000>, // GICD
198 <0x0 0x2f100000 0 0x200000>, // GICR
199 <0x0 0x2c000000 0 0x2000>, // GICC
200 <0x0 0x2c010000 0 0x2000>, // GICH
201 <0x0 0x2c02f000 0 0x2000>; // GICV
207 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
231 #address-cells = <0x3>;
232 #size-cells = <0x2>;
233 #interrupt-cells = <0x1>;
236 bus-range = <0x0 0x1>;
237 reg = <0x0 0x40000000 0x0 0x10000000>;
238 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
239 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
240 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
241 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
242 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
244 msi-map = <0x0 &its 0x0 0x10000>;
245 iommu-map = <0x0 &smmu 0x0 0x10000>;
253 reg = <0x0 0x2b400000 0x0 0x100000>;
261 msi-parent = <&its 0x10000>;
275 interrupt-map-mask = <0 0 63>;
276 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
277 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
279 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
280 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
281 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
282 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
283 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
284 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
285 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
286 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
287 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
288 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
289 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
290 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
291 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
292 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
293 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
294 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
295 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
296 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
297 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
298 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
299 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
300 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
301 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
302 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
303 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
304 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
305 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
306 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
307 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
308 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
309 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
310 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
311 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
312 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
313 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
314 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
315 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
316 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
317 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
318 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
319 <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
320 <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
321 <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;