dts/arm/foundation-v8.dtsi

1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 	model = "Foundation-v8A";
16 	compatible = "arm,foundation-aarch64", "arm,vexpress";
17 	interrupt-parent = <&gic>;
18 	#address-cells = <2>;
19 	#size-cells = <2>;
22 		stdout-path = "serial0:115200n8";
33 		#address-cells = <2>;
34 		#size-cells = <0>;
40 			next-level-cache = <&L2_0>;
46 			next-level-cache = <&L2_0>;
52 			next-level-cache = <&L2_0>;
58 			next-level-cache = <&L2_0>;
61 		L2_0: l2-cache0 {
63 			cache-level = <2>;
64 			cache-unified;
68 	memory@80000000 {
69 		device_type = "memory";
75 		compatible = "arm,armv8-timer";
80 		clock-frequency = <100000000>;
84 		compatible = "arm,armv8-pmuv3";
91 	spe-pmu {
92 		compatible = "arm,statistical-profiling-extension-v1";
97 		compatible = "arm,sbsa-gwdt";
101 		timeout-sec = <30>;
104 	v2m_clk24mhz: clock-24000000 {
105 		compatible = "fixed-clock";
106 		#clock-cells = <0>;
107 		clock-frequency = <24000000>;
108 		clock-output-names = "v2m:clk24mhz";
111 	v2m_refclk1mhz: clock-1000000 {
112 		compatible = "fixed-clock";
113 		#clock-cells = <0>;
114 		clock-frequency = <1000000>;
115 		clock-output-names = "v2m:refclk1mhz";
118 	v2m_refclk32khz: clock-32768 {
119 		compatible = "fixed-clock";
120 		#clock-cells = <0>;
121 		clock-frequency = <32768>;
122 		clock-output-names = "v2m:refclk32khz";
126 		compatible = "arm,vexpress,v2m-p1", "simple-bus";
127 		#address-cells = <2>; /* SMB chipselect number and offset */
128 		#size-cells = <1>;
137 		#interrupt-cells = <1>;
138 		interrupt-map-mask = <0 0 63>;
139 		interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
189 		iofpga-bus@300000000 {
190 			compatible = "simple-bus";
191 			#address-cells = <1>;
192 			#size-cells = <1>;
196 				compatible = "arm,vexpress-sysreg";
205 				clock-names = "uartclk", "apb_pclk";
213 				clock-names = "uartclk", "apb_pclk";
221 				clock-names = "uartclk", "apb_pclk";
229 				clock-names = "uartclk", "apb_pclk";