Lines Matching +full:mac +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
30 enable-method = "spin-table";
31 cpu-release-addr = <0x1 0x0000fff8>;
32 next-level-cache = <&xgene_L2_0>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x1 0x0000fff8>;
40 next-level-cache = <&xgene_L2_1>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 next-level-cache = <&xgene_L2_2>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
70 enable-method = "spin-table";
71 cpu-release-addr = <0x1 0x0000fff8>;
72 next-level-cache = <&xgene_L2_3>;
78 enable-method = "spin-table";
79 cpu-release-addr = <0x1 0x0000fff8>;
80 next-level-cache = <&xgene_L2_3>;
82 xgene_L2_0: l2-cache-0 {
84 cache-level = <2>;
85 cache-unified;
87 xgene_L2_1: l2-cache-1 {
89 cache-level = <2>;
90 cache-unified;
92 xgene_L2_2: l2-cache-2 {
94 cache-level = <2>;
95 cache-unified;
97 xgene_L2_3: l2-cache-3 {
99 cache-level = <2>;
100 cache-unified;
104 gic: interrupt-controller@78010000 {
105 compatible = "arm,cortex-a15-gic";
106 #interrupt-cells = <3>;
107 interrupt-controller;
116 compatible = "fixed-clock";
117 #clock-cells = <1>;
118 clock-frequency = <100000000>;
119 clock-output-names = "refclk";
123 compatible = "arm,armv8-timer";
125 <1 13 0xff08>, /* Non-secure Phys IRQ */
128 clock-frequency = <50000000>;
132 compatible = "apm,potenza-pmu";
137 compatible = "simple-bus";
138 #address-cells = <2>;
139 #size-cells = <2>;
141 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
144 #address-cells = <2>;
145 #size-cells = <2>;
149 compatible = "apm,xgene-pcppll-clock";
150 #clock-cells = <1>;
152 clock-names = "pcppll";
154 clock-output-names = "pcppll";
159 compatible = "apm,xgene-socpll-clock";
160 #clock-cells = <1>;
162 clock-names = "socpll";
164 clock-output-names = "socpll";
169 compatible = "fixed-factor-clock";
170 #clock-cells = <1>;
172 clock-names = "socplldiv2";
173 clock-mult = <1>;
174 clock-div = <2>;
175 clock-output-names = "socplldiv2";
179 compatible = "apm,xgene-device-clock";
180 #clock-cells = <1>;
183 reg-names = "div-reg";
184 divider-offset = <0x164>;
185 divider-width = <0x5>;
186 divider-shift = <0x0>;
187 clock-output-names = "ahbclk";
191 compatible = "apm,xgene-device-clock";
192 #clock-cells = <1>;
196 reg-names = "csr-reg", "div-reg";
197 csr-offset = <0x0>;
198 csr-mask = <0x2>;
199 enable-offset = <0x8>;
200 enable-mask = <0x2>;
201 divider-offset = <0x178>;
202 divider-width = <0x8>;
203 divider-shift = <0x0>;
204 clock-output-names = "sdioclk";
208 compatible = "apm,xgene-device-clock";
209 #clock-cells = <1>;
211 clock-names = "ethclk";
213 reg-names = "div-reg";
214 divider-offset = <0x238>;
215 divider-width = <0x9>;
216 divider-shift = <0x0>;
217 clock-output-names = "ethclk";
221 compatible = "apm,xgene-device-clock";
222 #clock-cells = <1>;
225 reg-names = "csr-reg";
226 clock-output-names = "menetclk";
230 compatible = "apm,xgene-device-clock";
231 #clock-cells = <1>;
234 reg-names = "csr-reg";
235 csr-mask = <0xa>;
236 enable-mask = <0xf>;
237 clock-output-names = "sge0clk";
241 compatible = "apm,xgene-device-clock";
242 #clock-cells = <1>;
245 reg-names = "csr-reg";
246 csr-mask = <0x3>;
247 clock-output-names = "xge0clk";
251 compatible = "apm,xgene-device-clock";
253 #clock-cells = <1>;
256 reg-names = "csr-reg";
257 csr-mask = <0x3>;
258 clock-output-names = "xge1clk";
262 compatible = "apm,xgene-device-clock";
263 #clock-cells = <1>;
266 reg-names = "csr-reg";
267 clock-output-names = "sataphy1clk";
269 csr-offset = <0x4>;
270 csr-mask = <0x00>;
271 enable-offset = <0x0>;
272 enable-mask = <0x06>;
276 compatible = "apm,xgene-device-clock";
277 #clock-cells = <1>;
280 reg-names = "csr-reg";
281 clock-output-names = "sataphy2clk";
283 csr-offset = <0x4>;
284 csr-mask = <0x3a>;
285 enable-offset = <0x0>;
286 enable-mask = <0x06>;
290 compatible = "apm,xgene-device-clock";
291 #clock-cells = <1>;
294 reg-names = "csr-reg";
295 clock-output-names = "sataphy3clk";
297 csr-offset = <0x4>;
298 csr-mask = <0x3a>;
299 enable-offset = <0x0>;
300 enable-mask = <0x06>;
304 compatible = "apm,xgene-device-clock";
305 #clock-cells = <1>;
308 reg-names = "csr-reg";
309 clock-output-names = "sata01clk";
310 csr-offset = <0x4>;
311 csr-mask = <0x05>;
312 enable-offset = <0x0>;
313 enable-mask = <0x39>;
317 compatible = "apm,xgene-device-clock";
318 #clock-cells = <1>;
321 reg-names = "csr-reg";
322 clock-output-names = "sata23clk";
323 csr-offset = <0x4>;
324 csr-mask = <0x05>;
325 enable-offset = <0x0>;
326 enable-mask = <0x39>;
330 compatible = "apm,xgene-device-clock";
331 #clock-cells = <1>;
334 reg-names = "csr-reg";
335 clock-output-names = "sata45clk";
336 csr-offset = <0x4>;
337 csr-mask = <0x05>;
338 enable-offset = <0x0>;
339 enable-mask = <0x39>;
343 compatible = "apm,xgene-device-clock";
344 #clock-cells = <1>;
347 reg-names = "csr-reg";
348 csr-offset = <0xc>;
349 csr-mask = <0x2>;
350 enable-offset = <0x10>;
351 enable-mask = <0x2>;
352 clock-output-names = "rtcclk";
356 compatible = "apm,xgene-device-clock";
357 #clock-cells = <1>;
360 reg-names = "csr-reg";
361 csr-offset = <0xc>;
362 csr-mask = <0x10>;
363 enable-offset = <0x10>;
364 enable-mask = <0x10>;
365 clock-output-names = "rngpkaclk";
370 compatible = "apm,xgene-device-clock";
371 #clock-cells = <1>;
374 reg-names = "csr-reg";
375 clock-output-names = "pcie0clk";
380 compatible = "apm,xgene-device-clock";
381 #clock-cells = <1>;
384 reg-names = "csr-reg";
385 clock-output-names = "pcie1clk";
390 compatible = "apm,xgene-device-clock";
391 #clock-cells = <1>;
394 reg-names = "csr-reg";
395 clock-output-names = "pcie2clk";
400 compatible = "apm,xgene-device-clock";
401 #clock-cells = <1>;
404 reg-names = "csr-reg";
405 clock-output-names = "pcie3clk";
410 compatible = "apm,xgene-device-clock";
411 #clock-cells = <1>;
414 reg-names = "csr-reg";
415 clock-output-names = "pcie4clk";
419 compatible = "apm,xgene-device-clock";
420 #clock-cells = <1>;
423 reg-names = "csr-reg";
424 clock-output-names = "dmaclk";
429 compatible = "apm,xgene1-msi";
430 msi-controller;
450 scu: system-clk-controller@17000000 {
451 compatible = "apm,xgene-scu","syscon";
456 compatible = "syscon-reboot";
463 compatible = "apm,xgene-csw", "syscon";
468 compatible = "apm,xgene-mcb", "syscon";
473 compatible = "apm,xgene-mcb", "syscon";
478 compatible = "apm,xgene-efuse", "syscon";
483 compatible = "apm,xgene-rb", "syscon";
488 compatible = "apm,xgene-edac";
489 #address-cells = <2>;
490 #size-cells = <2>;
492 regmap-csw = <&csw>;
493 regmap-mcba = <&mcba>;
494 regmap-mcbb = <&mcbb>;
495 regmap-efuse = <&efuse>;
496 regmap-rb = <&rb>;
503 compatible = "apm,xgene-edac-mc";
505 memory-controller = <0>;
509 compatible = "apm,xgene-edac-mc";
511 memory-controller = <1>;
515 compatible = "apm,xgene-edac-mc";
517 memory-controller = <2>;
521 compatible = "apm,xgene-edac-mc";
523 memory-controller = <3>;
527 compatible = "apm,xgene-edac-pmd";
529 pmd-controller = <0>;
533 compatible = "apm,xgene-edac-pmd";
535 pmd-controller = <1>;
539 compatible = "apm,xgene-edac-pmd";
541 pmd-controller = <2>;
545 compatible = "apm,xgene-edac-pmd";
547 pmd-controller = <3>;
551 compatible = "apm,xgene-edac-l3";
556 compatible = "apm,xgene-edac-soc-v1";
562 compatible = "apm,xgene-pmu-v2";
563 #address-cells = <2>;
564 #size-cells = <2>;
566 regmap-csw = <&csw>;
567 regmap-mcba = <&mcba>;
568 regmap-mcbb = <&mcbb>;
573 compatible = "apm,xgene-pmu-l3c";
578 compatible = "apm,xgene-pmu-iob";
583 compatible = "apm,xgene-pmu-mcb";
585 enable-bit-index = <0>;
589 compatible = "apm,xgene-pmu-mcb";
591 enable-bit-index = <1>;
595 compatible = "apm,xgene-pmu-mc";
597 enable-bit-index = <0>;
601 compatible = "apm,xgene-pmu-mc";
603 enable-bit-index = <1>;
607 compatible = "apm,xgene-pmu-mc";
609 enable-bit-index = <2>;
613 compatible = "apm,xgene-pmu-mc";
615 enable-bit-index = <3>;
622 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
623 #interrupt-cells = <1>;
624 #size-cells = <2>;
625 #address-cells = <3>;
628 reg-names = "csr", "cfg";
632 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
634 bus-range = <0x00 0xff>;
635 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
636 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
640 dma-coherent;
642 msi-parent = <&msi>;
648 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
649 #interrupt-cells = <1>;
650 #size-cells = <2>;
651 #address-cells = <3>;
654 reg-names = "csr", "cfg";
658 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
660 bus-range = <0x00 0xff>;
661 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
662 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
666 dma-coherent;
668 msi-parent = <&msi>;
674 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
675 #interrupt-cells = <1>;
676 #size-cells = <2>;
677 #address-cells = <3>;
680 reg-names = "csr", "cfg";
684 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
686 bus-range = <0x00 0xff>;
687 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
688 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
692 dma-coherent;
694 msi-parent = <&msi>;
700 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
701 #interrupt-cells = <1>;
702 #size-cells = <2>;
703 #address-cells = <3>;
706 reg-names = "csr", "cfg";
710 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
712 bus-range = <0x00 0xff>;
713 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
714 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
718 dma-coherent;
720 msi-parent = <&msi>;
726 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
727 #interrupt-cells = <1>;
728 #size-cells = <2>;
729 #address-cells = <3>;
732 reg-names = "csr", "cfg";
736 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
738 bus-range = <0x00 0xff>;
739 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
740 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
744 dma-coherent;
746 msi-parent = <&msi>;
750 compatible = "apm,xgene-slimpro-mbox";
752 #mbox-cells = <1>;
764 compatible = "apm,xgene-slimpro-i2c";
769 compatible = "apm,xgene-slimpro-hwmon";
777 reg-shift = <2>;
778 clock-frequency = <10000000>; /* Updated by bootloader */
779 interrupt-parent = <&gic>;
787 reg-shift = <2>;
788 clock-frequency = <10000000>; /* Updated by bootloader */
789 interrupt-parent = <&gic>;
797 reg-shift = <2>;
798 clock-frequency = <10000000>; /* Updated by bootloader */
799 interrupt-parent = <&gic>;
807 reg-shift = <2>;
808 clock-frequency = <10000000>; /* Updated by bootloader */
809 interrupt-parent = <&gic>;
814 compatible = "arasan,sdhci-4.9a";
817 dma-coherent;
818 no-1-8-v;
819 clock-names = "clk_xin", "clk_ahb";
824 compatible = "apm,xgene-gpio";
826 gpio-controller;
827 #gpio-cells = <2>;
831 compatible = "snps,dw-apb-gpio";
833 #address-cells = <1>;
834 #size-cells = <0>;
836 porta: gpio-controller@0 {
837 compatible = "snps,dw-apb-gpio-port";
838 gpio-controller;
839 #gpio-cells = <2>;
840 snps,nr-gpios = <32>;
847 #address-cells = <1>;
848 #size-cells = <0>;
849 compatible = "snps,designware-i2c";
852 #clock-cells = <1>;
858 compatible = "apm,xgene-phy";
860 #phy-cells = <1>;
863 apm,tx-boost-gain = <30 30 30 30 30 30>;
864 apm,tx-eye-tuning = <2 10 10 2 10 10>;
868 compatible = "apm,xgene-phy";
870 #phy-cells = <1>;
873 apm,tx-boost-gain = <30 30 30 30 30 30>;
874 apm,tx-eye-tuning = <1 10 10 2 10 10>;
878 compatible = "apm,xgene-phy";
880 #phy-cells = <1>;
883 apm,tx-boost-gain = <31 31 31 31 31 31>;
884 apm,tx-eye-tuning = <2 10 10 2 10 10>;
888 compatible = "apm,xgene-ahci";
895 dma-coherent;
899 phy-names = "sata-phy";
903 compatible = "apm,xgene-ahci";
910 dma-coherent;
914 phy-names = "sata-phy";
918 compatible = "apm,xgene-ahci";
924 dma-coherent;
928 phy-names = "sata-phy";
931 /* Node-name might need to be coded as dwusb for backward compatibility */
937 dma-coherent;
946 dma-coherent;
951 compatible = "apm,xgene-gpio-sb";
953 #gpio-cells = <2>;
954 gpio-controller;
961 interrupt-parent = <&gic>;
962 #interrupt-cells = <2>;
963 interrupt-controller;
967 compatible = "apm,xgene-rtc";
970 #clock-cells = <1>;
975 compatible = "apm,xgene-mdio-rgmii";
976 #address-cells = <1>;
977 #size-cells = <0>;
983 compatible = "apm,xgene-enet";
988 reg-names = "enet_csr", "ring_csr", "ring_cmd";
990 dma-coherent;
992 /* mac address will be overwritten by the bootloader */
993 local-mac-address = [00 00 00 00 00 00];
994 phy-connection-type = "rgmii";
995 phy-handle = <&menetphy>,<&menet0phy>;
997 compatible = "apm,xgene-mdio";
998 #address-cells = <1>;
999 #size-cells = <0>;
1000 menetphy: ethernet-phy@3 {
1001 compatible = "ethernet-phy-id001c.c915";
1009 compatible = "apm,xgene1-sgenet";
1014 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1017 dma-coherent;
1019 local-mac-address = [00 00 00 00 00 00];
1020 phy-connection-type = "sgmii";
1021 phy-handle = <&sgenet0phy>;
1025 compatible = "apm,xgene1-sgenet";
1030 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1033 port-id = <1>;
1034 dma-coherent;
1035 local-mac-address = [00 00 00 00 00 00];
1036 phy-connection-type = "sgmii";
1037 phy-handle = <&sgenet1phy>;
1041 compatible = "apm,xgene1-xgenet";
1046 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1056 dma-coherent;
1058 /* mac address will be overwritten by the bootloader */
1059 local-mac-address = [00 00 00 00 00 00];
1060 phy-connection-type = "xgmii";
1064 compatible = "apm,xgene1-xgenet";
1069 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1072 port-id = <1>;
1073 dma-coherent;
1075 /* mac address will be overwritten by the bootloader */
1076 local-mac-address = [00 00 00 00 00 00];
1077 phy-connection-type = "xgmii";
1081 compatible = "apm,xgene-rng";
1088 compatible = "apm,xgene-storm-dma";
1099 dma-coherent;