Lines Matching full:clkc
8 #include <dt-bindings/clock/g12a-clkc.h>
36 clocks = <&clkc CLKID_HDMI>,
37 <&clkc CLKID_HTX_PCLK>,
38 <&clkc CLKID_VPU_INTR>;
46 clocks = <&clkc CLKID_HDMI>,
47 <&clkc CLKID_HTX_PCLK>,
48 <&clkc CLKID_VPU_INTR>;
55 clocks = <&clkc CLKID_EFUSE>;
153 clocks = <&clkc CLKID_PCIE_PHY
154 &clkc CLKID_PCIE_COMB
155 &clkc CLKID_PCIE_PLL>;
177 clocks = <&clkc CLKID_ETH>,
178 <&clkc CLKID_FCLK_DIV2>,
179 <&clkc CLKID_MPLL2>,
180 <&clkc CLKID_FCLK_DIV2>;
209 clocks = <&clkc CLKID_HDMI>,
210 <&clkc CLKID_HTX_PCLK>,
211 <&clkc CLKID_VPU_INTR>;
218 assigned-clocks = <&clkc CLKID_HDMI_SEL>,
219 <&clkc CLKID_HDMI>;
248 clocks = <&clkc CLKID_RNG0>;
258 clocks = <&clkc CLKID_AUDIO_CODEC>;
1553 clocks = <&clkc CLKID_TS>;
1563 clocks = <&clkc CLKID_TS>;
1618 clkc: clock-controller { label
1619 compatible = "amlogic,g12a-clkc";
1643 clocks = <&clkc CLKID_VPU>,
1644 <&clkc CLKID_VAPB>;
1652 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1653 <&clkc CLKID_VPU_0>,
1654 <&clkc CLKID_VPU>, /* Glitch free mux */
1655 <&clkc CLKID_VAPB_0_SEL>,
1656 <&clkc CLKID_VAPB_0>,
1657 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1658 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1660 <&clkc CLKID_VPU_0>,
1661 <&clkc CLKID_FCLK_DIV4>,
1663 <&clkc CLKID_VAPB_0>;
1683 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1696 clocks = <&clkc CLKID_PCIE_PLL>;
1700 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1708 clocks = <&clkc CLKID_ETH_PHY>,
1710 <&clkc CLKID_MPLL_50M>;
1754 clocks = <&xtal>, <&clkc CLKID_CLK81>;
2098 clocks = <&clkc CLKID_I2C>;
2142 clocks = <&clkc CLKID_PARSER>,
2143 <&clkc CLKID_DOS>,
2144 <&clkc CLKID_VDEC_1>,
2145 <&clkc CLKID_VDEC_HEVC>,
2146 <&clkc CLKID_VDEC_HEVCF>;
2227 clocks = <&clkc CLKID_MIPI_DSI_HOST>,
2228 <&clkc CLKID_MIPI_DSI_PXCLK>,
2229 <&clkc CLKID_CTS_ENCL>;
2237 assigned-clocks = <&clkc CLKID_MIPI_DSI_PXCLK_SEL>,
2238 <&clkc CLKID_CTS_ENCL_SEL>,
2239 <&clkc CLKID_VCLK2_SEL>;
2240 assigned-clock-parents = <&clkc CLKID_GP0_PLL>,
2241 <&clkc CLKID_VCLK2_DIV1>,
2242 <&clkc CLKID_GP0_PLL>;
2274 clocks = <&clkc CLKID_SPICC0>,
2275 <&clkc CLKID_SPICC0_SCLK>;
2286 clocks = <&clkc CLKID_SPICC1>,
2287 <&clkc CLKID_SPICC1_SCLK>;
2300 clocks = <&clkc CLKID_CLK81>;
2331 clocks = <&clkc CLKID_I2C>;
2341 clocks = <&clkc CLKID_I2C>;
2351 clocks = <&clkc CLKID_I2C>;
2361 clocks = <&clkc CLKID_I2C>;
2374 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2384 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2394 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2406 clocks = <&clkc CLKID_SD_EMMC_A>,
2407 <&clkc CLKID_SD_EMMC_A_CLK0>,
2408 <&clkc CLKID_FCLK_DIV2>;
2418 clocks = <&clkc CLKID_SD_EMMC_B>,
2419 <&clkc CLKID_SD_EMMC_B_CLK0>,
2420 <&clkc CLKID_FCLK_DIV2>;
2430 clocks = <&clkc CLKID_SD_EMMC_C>,
2431 <&clkc CLKID_SD_EMMC_C_CLK0>,
2432 <&clkc CLKID_FCLK_DIV2>;
2446 clocks = <&clkc CLKID_USB>;
2459 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2488 clocks = <&clkc CLKID_MALI>;
2574 clocks = <&clkc CLKID_NNA_CORE_CLK>,
2575 <&clkc CLKID_NNA_AXI_CLK>;
2577 assigned-clocks = <&clkc CLKID_NNA_CORE_CLK>,
2578 <&clkc CLKID_NNA_AXI_CLK>;