Lines Matching +full:0 +full:x2800
20 #clock-cells = <0>;
25 #clock-cells = <0>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
64 reg = <0x0 0x400 0x0 0x100>;
67 #size-cells = <0>;
75 reg = <0x0 0x1400 0x0 0x100>;
83 reg = <0x0 0x2400 0x0 0x400>,
84 <0x0 0x7fff0000 0x0 0x1000>;
86 #size-cells = <0>;
87 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
91 cdns,trigger-address = <0x7fff0000>;
97 reg = <0x0 0x2800 0x0 0x100>;
99 #size-cells = <0>;
109 reg = <0x0 0x4000 0x0 0x78>;
111 #size-cells = <0>;
114 porta: gpio-port@0 {
116 reg = <0>;
137 reg = <0x0 0x4800 0x0 0x100>;
146 reg = <0x0 0x800000 0x0 0x200000>, /* GICD */
147 <0x0 0xa00000 0x0 0x200000>, /* GICR */
148 <0x0 0x60000000 0x0 0x2000>, /* GICC */
149 <0x0 0x60010000 0x0 0x1000>, /* GICH */
150 <0x0 0x60020000 0x0 0x2000>; /* GICV */
164 reg = <0x0 0x820000 0x0 0x10000>;
168 <0xc00000 0x1000000>;
174 reg = <0x0 0x30440000 0x0 0x10000>,
175 <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */
178 cdns,phy-input-delay-sd-highspeed = <0x4>;
179 cdns,phy-input-delay-legacy = <0x4>;
180 cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
181 cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
188 reg = <0x0 0x307c0000 0x0 0x3000>;