dts/amd/amd-seattle-soc.dtsi

1 // SPDX-License-Identifier: GPL-2.0
10 	interrupt-parent = <&gic0>;
11 	#address-cells = <2>;
12 	#size-cells = <2>;
14 	gic0: interrupt-controller@e1101000 {
15 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 		interrupt-controller;
17 		#interrupt-cells = <3>;
18 		#address-cells = <2>;
19 		#size-cells = <2>;
26 		v2m0: v2m@e0080000 {
27 			compatible = "arm,gic-v2m-frame";
28 			msi-controller;
34 		compatible = "arm,armv8-timer";
42 		compatible = "simple-bus";
43 		#address-cells = <2>;
44 		#size-cells = <2>;
48 		 * dma-ranges is 40-bit address space containing:
49 		 * - GICv2m MSI register is at 0xe0080000
50 		 * - DRAM range [0x8000000000 to 0xffffffffff]
52 		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
54 		/include/ "amd-seattle-clks.dtsi"
57 			compatible = "snps,dwc-ahci";
62 			dma-coherent;
68 			compatible = "snps,dwc-ahci";
75 			dma-coherent;
79 			compatible = "arm,mmu-401";
81 			#global-interrupts = <1>;
83 			#iommu-cells = <2>;
84 			dma-coherent;
88 			compatible = "arm,mmu-401";
90 			#global-interrupts = <1>;
92 			#iommu-cells = <1>;
93 			dma-coherent;
98 			compatible = "snps,designware-i2c";
106 			compatible = "snps,designware-i2c";
117 			clock-names = "uartclk", "apb_pclk";
124 			spi-controller;
127 			clock-names = "apb_pclk";
134 			spi-controller;
137 			clock-names = "apb_pclk";
138 			num-cs = <1>;
139 			#address-cells = <1>;
140 			#size-cells = <0>;
146 			#gpio-cells = <2>;
148 			gpio-controller;
150 			interrupt-controller;
151 			#interrupt-cells = <2>;
153 			clock-names = "apb_pclk";
159 			#gpio-cells = <2>;
161 			gpio-controller;
162 			interrupt-controller;
163 			#interrupt-cells = <2>;
166 			clock-names = "apb_pclk";
172 			#gpio-cells = <2>;
174 			gpio-controller;
175 			interrupt-controller;
176 			#interrupt-cells = <2>;
179 			clock-names = "apb_pclk";
185 			#gpio-cells = <2>;
187 			gpio-controller;
188 			interrupt-controller;
189 			#interrupt-cells = <2>;
192 			clock-names = "apb_pclk";
198 			#gpio-cells = <2>;
200 			gpio-controller;
201 			interrupt-controller;
202 			#interrupt-cells = <2>;
205 			clock-names = "apb_pclk";
210 			compatible = "amd,ccp-seattle-v1a";
213 			dma-coherent;
221 			compatible = "pci-host-ecam-generic";
222 			#address-cells = <3>;
223 			#size-cells = <2>;
224 			#interrupt-cells = <1>;
226 			bus-range = <0 0x7f>;
227 			msi-parent = <&v2m0>;
230 			interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
231 			interrupt-map =
247 			dma-coherent;
248 			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
250 				/* I/O Memory (size=64K) */
252 				/* 32-bit MMIO (size=2G) */
254 				/* 64-bit MMIO (size= 508G) */
256 			iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
260 			compatible = "arm,mmu-401";
262 			#global-interrupts = <1>;
264 			#iommu-cells = <1>;
265 			dma-coherent;
270 			compatible = "arm,ccn-504";
277 			compatible = "ipmi-kcs";
281 			reg-size = <1>;
282 			reg-spacing = <4>;