Lines Matching +full:dw +full:- +full:apb +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a53";
25 enable-method = "psci";
29 compatible = "arm,cortex-a53";
32 enable-method = "psci";
36 compatible = "arm,cortex-a53";
39 enable-method = "psci";
43 compatible = "arm,cortex-a53";
46 enable-method = "psci";
51 compatible = "arm,psci-1.0";
55 dcxo24M: dcxo24M-clk {
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 clock-output-names = "dcxo24M";
59 #clock-cells = <0>;
62 iosc: internal-osc-clk {
63 compatible = "fixed-clock";
64 clock-frequency = <16000000>;
65 clock-accuracy = <300000000>;
66 clock-output-names = "iosc";
67 #clock-cells = <0>;
70 osc32k: osc32k-clk {
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 clock-output-names = "osc32k";
74 #clock-cells = <0>;
78 compatible = "arm,armv8-timer";
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
96 compatible = "allwinner,sun50i-a100-ccu";
99 clock-names = "hosc", "losc", "iosc";
100 #clock-cells = <1>;
101 #reset-cells = <1>;
104 dma: dma-controller@3002000 {
105 compatible = "allwinner,sun50i-a100-dma";
109 clock-names = "bus", "mbus";
111 dma-channels = <8>;
112 dma-requests = <52>;
113 #dma-cells = <1>;
116 gic: interrupt-controller@3021000 {
117 compatible = "arm,gic-400";
122 interrupt-controller;
123 #interrupt-cells = <3>;
127 compatible = "allwinner,sun50i-a100-sid",
128 "allwinner,sun50i-a64-sid";
130 #address-cells = <1>;
131 #size-cells = <1>;
139 compatible = "allwinner,sun50i-a100-pinctrl";
149 clock-names = "apb", "hosc", "losc";
150 gpio-controller;
151 #gpio-cells = <3>;
152 interrupt-controller;
153 #interrupt-cells = <3>;
155 uart0_pb_pins: uart0-pb-pins {
162 compatible = "snps,dw-apb-uart";
165 reg-shift = <2>;
166 reg-io-width = <4>;
173 compatible = "snps,dw-apb-uart";
176 reg-shift = <2>;
177 reg-io-width = <4>;
184 compatible = "snps,dw-apb-uart";
187 reg-shift = <2>;
188 reg-io-width = <4>;
195 compatible = "snps,dw-apb-uart";
198 reg-shift = <2>;
199 reg-io-width = <4>;
206 compatible = "snps,dw-apb-uart";
209 reg-shift = <2>;
210 reg-io-width = <4>;
217 compatible = "allwinner,sun50i-a100-i2c",
218 "allwinner,sun8i-v536-i2c",
219 "allwinner,sun6i-a31-i2c";
225 dma-names = "rx", "tx";
227 #address-cells = <1>;
228 #size-cells = <0>;
232 compatible = "allwinner,sun50i-a100-i2c",
233 "allwinner,sun8i-v536-i2c",
234 "allwinner,sun6i-a31-i2c";
240 dma-names = "rx", "tx";
242 #address-cells = <1>;
243 #size-cells = <0>;
247 compatible = "allwinner,sun50i-a100-i2c",
248 "allwinner,sun8i-v536-i2c",
249 "allwinner,sun6i-a31-i2c";
255 dma-names = "rx", "tx";
257 #address-cells = <1>;
258 #size-cells = <0>;
262 compatible = "allwinner,sun50i-a100-i2c",
263 "allwinner,sun8i-v536-i2c",
264 "allwinner,sun6i-a31-i2c";
270 dma-names = "rx", "tx";
272 #address-cells = <1>;
273 #size-cells = <0>;
276 ths: thermal-sensor@5070400 {
277 compatible = "allwinner,sun50i-a100-ths";
281 clock-names = "bus";
283 nvmem-cells = <&ths_calibration>;
284 nvmem-cell-names = "calibration";
285 #thermal-sensor-cells = <1>;
289 compatible = "allwinner,sun50i-a100-r-ccu";
293 clock-names = "hosc", "losc", "iosc", "pll-periph";
294 #clock-cells = <1>;
295 #reset-cells = <1>;
298 r_intc: interrupt-controller@7010320 {
299 compatible = "allwinner,sun50i-a100-nmi",
300 "allwinner,sun9i-a80-nmi";
301 interrupt-controller;
302 #interrupt-cells = <2>;
308 compatible = "allwinner,sun50i-a100-r-pinctrl";
312 clock-names = "apb", "hosc", "losc";
313 gpio-controller;
314 #gpio-cells = <3>;
315 interrupt-controller;
316 #interrupt-cells = <3>;
318 r_i2c0_pins: r-i2c0-pins {
323 r_i2c1_pins: r-i2c1-pins {
330 compatible = "snps,dw-apb-uart";
333 reg-shift = <2>;
334 reg-io-width = <4>;
341 compatible = "allwinner,sun50i-a100-i2c",
342 "allwinner,sun8i-v536-i2c",
343 "allwinner,sun6i-a31-i2c";
349 dma-names = "rx", "tx";
350 pinctrl-names = "default";
351 pinctrl-0 = <&r_i2c0_pins>;
353 #address-cells = <1>;
354 #size-cells = <0>;
358 compatible = "allwinner,sun50i-a100-i2c",
359 "allwinner,sun8i-v536-i2c",
360 "allwinner,sun6i-a31-i2c";
366 dma-names = "rx", "tx";
367 pinctrl-names = "default";
368 pinctrl-0 = <&r_i2c1_pins>;
370 #address-cells = <1>;
371 #size-cells = <0>;
375 thermal-zones {
376 cpu-thermal {
377 polling-delay-passive = <0>;
378 polling-delay = <0>;
379 thermal-sensors = <&ths 0>;
382 ddr-thermal {
383 polling-delay-passive = <0>;
384 polling-delay = <0>;
385 thermal-sensors = <&ths 2>;
388 gpu-thermal {
389 polling-delay-passive = <0>;
390 polling-delay = <0>;
391 thermal-sensors = <&ths 1>;