Lines Matching full:workaround
450 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
473 The workaround promotes data cache clean instructions to
475 Please note that this does not necessarily enable the workaround,
495 The workaround promotes data cache clean instructions to
497 Please note that this does not necessarily enable the workaround,
518 The workaround promotes data cache clean instructions to
521 workaround, as it depends on the alternative framework, which will
540 The workaround promotes data cache clean instructions to
542 Please note that this does not necessarily enable the workaround,
558 The workaround is to promote device loads to use Load-Acquire
560 Please note that this does not necessarily enable the workaround,
578 The workaround is to verify that the Stage 1 translation
580 Please note that this does not necessarily enable the workaround,
592 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
615 The workaround is to write the contextidr_el1 register on exception
617 Please note that this does not necessarily enable the workaround,
641 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
645 without a break-before-make. The workaround is to disable the usage
656 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
673 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
699 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
714 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
730 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
739 workaround repeats the TLBI+DSB operation.
747 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
762 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
764 This option adds a workaround for ARM Neoverse-N1 erratum
768 modified by another CPU. The workaround depends on a firmware
771 Workaround the issue by hiding the DIC feature from EL0. This
777 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
780 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
784 non-cacheable memory attributes. The workaround depends on a firmware
787 KVM guests must also have the workaround implemented or they can
803 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
805 hardware update of the page table's dirty bit. The workaround
811 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
814 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
831 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
841 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
846 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
859 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
864 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
880 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
884 Enable workaround for ARM Cortex-A710 erratum 2054223
890 Workaround is to issue two TSB consecutively on affected cores.
895 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
899 Enable workaround for ARM Neoverse-N2 erratum 2067961
905 Workaround is to issue two TSB consecutively on affected cores.
913 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
918 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
931 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
936 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
952 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
965 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
969 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
983 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
987 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1006 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1010 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1024 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1028 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1041 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1044 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1051 mprotect() system call. Workaround the problem by doing a break-before-make
1060 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1064 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1074 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1078 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1088 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1091 This option adds the workaround for the following errata:
1131 Enable workaround for errata 22375 and 24313.
1210 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1220 The workaround is to ensure these bits are clear in TCR_ELx.
1221 The workaround only affects the Fujitsu-A64FX.
1298 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"