Lines Matching +full:synquacer +full:- +full:pre +full:- +full:its
1 # SPDX-License-Identifier: GPL-2.0-only
272 ARM 64-bit (AArch64) Linux support.
280 # required due to use of the -Zfixed-x18 flag.
283 # -Zsanitizer=shadow-call-stack flag.
293 depends on $(cc-option,-fpatchable-function-entry=2)
319 # VA_BITS - PAGE_SHIFT - 3
397 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
402 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
452 at stage-2.
460 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
465 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
468 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
474 data cache clean-and-invalidate.
482 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
487 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
496 data cache clean-and-invalidate.
504 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
509 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
512 If a Cortex-A53 processor is executing a store or prefetch for
519 data cache clean-and-invalidate.
527 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
532 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
541 data cache clean-and-invalidate.
549 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
553 erratum 832075 on Cortex-A57 parts up to r1p2.
555 Affected Cortex-A57 parts might deadlock when exclusive load/store
556 instructions to Write-Back memory are mixed with Device loads.
558 The workaround is to promote device loads to use Load-Acquire
567 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
571 erratum 834220 on Cortex-A57 parts up to r1p2.
573 Affected Cortex-A57 parts might report a Stage 2 translation
587 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
591 This option removes the AES hwcap for aarch32 user-space to
592 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
603 bool "Cortex-A53: 845719: a load might read incorrect data"
608 erratum 845719 on Cortex-A53 parts up to r0p4.
610 When running a compat (AArch32) userspace on an affected Cortex-A53
616 return to a 32-bit task.
624 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
627 This option links the kernel with '--fix-cortex-a53-843419' and
630 Cortex-A53 parts up to r0p4.
635 def_bool $(ld-option,--fix-cortex-a53-843419)
638 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
641 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
643 Affected Cortex-A55 cores (all revisions) could cause incorrect
645 without a break-before-make. The workaround is to disable the usage
652 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
656 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
659 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
669 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
673 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
675 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
682 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
686 This option adds work arounds for ARM Cortex-A57 erratum 1319537
689 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
695 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
699 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
701 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
711 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
714 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
716 Under very rare circumstances, affected Cortex-A55 CPUs
717 may not handle a race between a break-before-make sequence on one
727 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
730 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
732 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
736 break-before-make sequence, then under very rare circumstances
744 bool "Cortex-A76: Software Step might prevent interrupt recognition"
747 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
749 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
762 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
764 This option adds a workaround for ARM Neoverse-N1 erratum
767 Affected Neoverse-N1 cores could execute a stale instruction when
772 forces user-space to perform cache maintenance.
777 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
780 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
782 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
783 of a store-exclusive or read of PAR_EL1 and a load with device or
784 non-cacheable memory attributes. The workaround depends on a firmware
800 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
803 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
804 Affected Cortex-A510 might not respect the ordering rules for
811 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
814 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
815 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
823 previous guest entry, and can be restored from the in-memory copy.
828 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
831 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
832 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
836 user-space should not be using these instructions.
841 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
846 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
848 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
859 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
864 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
866 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
880 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
884 Enable workaround for ARM Cortex-A710 erratum 2054223
895 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
899 Enable workaround for ARM Neoverse-N2 erratum 2067961
913 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
918 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
920 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
931 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
936 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
938 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
949 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
952 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
954 Under very rare circumstances, affected Cortex-A510 CPUs
955 may not handle a race between a break-before-make sequence on one
965 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
969 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
971 Affected Cortex-A510 core might fail to write into system registers after the
983 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
987 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
989 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1006 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1010 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1012 Affected Cortex-A510 core might cause trace data corruption, when being written
1024 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1028 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1031 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1041 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1044 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1046 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1047 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1050 Only user-space does executable to non-executable permission transition via
1051 mprotect() system call. Workaround the problem by doing a break-before-make
1060 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1064 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1066 On an affected Cortex-A520 core, a speculatively executed unprivileged
1074 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1078 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1080 On an affected Cortex-A510 core, a speculatively executed unprivileged
1088 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1093 * ARM Cortex-A76 erratum 3324349
1094 * ARM Cortex-A77 erratum 3324348
1095 * ARM Cortex-A78 erratum 3324344
1096 * ARM Cortex-A78C erratum 3324346
1097 * ARM Cortex-A78C erratum 3324347
1098 * ARM Cortex-A710 erratam 3324338
1099 * ARM Cortex-A715 errartum 3456084
1100 * ARM Cortex-A720 erratum 3456091
1101 * ARM Cortex-A725 erratum 3456106
1102 * ARM Cortex-X1 erratum 3324344
1103 * ARM Cortex-X1C erratum 3324346
1104 * ARM Cortex-X2 erratum 3324338
1105 * ARM Cortex-X3 erratum 3324335
1106 * ARM Cortex-X4 erratum 3194386
1107 * ARM Cortex-X925 erratum 3324334
1108 * ARM Neoverse-N1 erratum 3324349
1110 * ARM Neoverse-N3 erratum 3456111
1111 * ARM Neoverse-V1 erratum 3324341
1113 * ARM Neoverse-V3 erratum 3312417
1121 SSBS. The presence of the SSBS special-purpose register is hidden
1133 This implements two gicv3-its errata workarounds for ThunderX. Both
1134 with a small impact affecting only ITS table allocation.
1139 The fixes are in ITS initialization and basically ignore memory access
1145 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1149 ITS SYNC command hang for cross node io and collections/cpu mapping.
1173 contains data for a non-current ASID. The fix is to
1184 interrupts in host. Trapping both GICv3 group-0 and group-1
1207 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1210 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1211 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1221 The workaround only affects the Fujitsu-A64FX.
1230 when issued ITS commands such as VMOVP and VMAPP, and requires
1261 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1281 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1291 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1292 This means, that its sharability feature may not be used, even though it
1298 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1301 Socionext Synquacer SoCs implement a separate h/w block to generate
1302 MSI doorbell writes with non-zero values for the device ID.
1334 look-up. AArch32 emulation requires applications compiled
1348 bool "36-bit" if EXPERT
1352 bool "39-bit"
1356 bool "42-bit"
1360 bool "47-bit"
1364 bool "48-bit"
1367 bool "52-bit"
1370 Enable 52-bit virtual addressing for userspace when explicitly
1371 requested via a hint to mmap(). The kernel will also use 52-bit
1372 virtual addresses for its own mappings (provided HW support for
1373 this feature is available, otherwise it reverts to 48-bit).
1375 NOTE: Enabling 52-bit virtual addressing in conjunction with
1378 impact on its susceptibility to brute-force attacks.
1380 If unsure, select 48-bit virtual addressing instead.
1385 bool "Force 52-bit virtual addresses for userspace"
1388 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1389 to maintain compatibility with older software by providing 48-bit VAs
1392 This configuration option disables the 48-bit compatibility logic, and
1393 forces all userspace addresses to be 52-bit on HW that supports it. One
1414 bool "48-bit"
1418 bool "52-bit"
1422 Enable support for a 52-bit physical address space, introduced as
1423 part of the ARMv8.2-LPA extension.
1426 do not support ARMv8.2-LPA, but with some added memory overhead (and
1449 bool "Build big-endian kernel"
1450 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1453 Say Y if you plan on running a kernel with a big-endian userspace.
1456 bool "Build little-endian kernel"
1458 Say Y if you plan on running a kernel with a little-endian userspace.
1464 bool "Multi-core scheduler support"
1466 Multi-core scheduler support improves the CPU scheduler's decision
1467 making when dealing with multi-core CPU chips at a cost of slightly
1476 by sharing mid-level caches, last-level cache tags or internal
1487 int "Maximum number of CPUs (2-4096)"
1492 bool "Support for hot-pluggable CPUs"
1508 Enable NUMA (Non-Uniform Memory Access) support.
1536 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1605 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1608 # ----+-------------------+--------------+----------------------+-------------------------+
1636 Speculation attacks against some high-performance processors can
1648 Speculation attacks against some high-performance processors can
1650 When taking an exception from user-space, a sequence of branches
1657 Apply read-only attributes of VM areas to the linear alias of
1658 the backing pages as well. This prevents code or read-only data
1672 user-space memory directly by pointing TTBR0_EL1 to a reserved
1683 Documentation/arch/arm64/tagged-address-abi.rst.
1686 bool "Kernel support for 32-bit EL0"
1692 This option enables support for a 32-bit EL0 running under a 64-bit
1693 kernel at EL1. AArch32-specific components such as system calls,
1701 If you want to execute 32-bit userspace applications, say Y.
1706 bool "Enable kuser helpers page for 32-bit applications"
1709 Warning: disabling this option may break 32-bit user programs.
1733 bool "Enable vDSO for 32-bit applications"
1739 Place in the process address space of 32-bit applications an
1743 You must have a 32-bit build of glibc 2.22 or later for programs
1747 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1751 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1752 otherwise with '-marm'.
1755 bool "Fix up misaligned multi-word loads and stores in user space"
1797 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1798 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1813 The SETEND instruction alters the data-endianness of the
1821 for this feature to be enabled. If a new CPU - which doesn't support mixed
1822 endian - is hotplugged in after this feature has been enabled, there could
1841 Similarly, writes to read-only pages with the DBM bit set will
1842 clear the read-only bit (AP[2]) instead of raising a
1846 to work on pre-ARMv8.1 hardware and the performance impact is
1854 prevents the kernel or hypervisor from accessing user-space (EL0)
1864 def_bool $(as-instr,.arch_extension lse)
1879 Say Y here to make use of these instructions for the in-kernel
1890 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1893 def_bool $(as-instr,.arch armv8.2-a+sha3)
1953 context-switched along with the process.
1976 If the compiler supports the -mbranch-protection or
1977 -msign-return-address flag (e.g. GCC 7 or later), then this option
1988 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1992 def_bool $(cc-option,-msign-return-address=all)
1995 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1998 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2001 def_bool $(as-instr,.arch_extension rcpc)
2031 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2038 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2049 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2092 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2108 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2112 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2128 architectural support for run-time, always-on detection of
2130 to eliminate vulnerabilities arising from memory-unsafe
2138 not be allowed a late bring-up.
2144 Documentation/arch/arm64/memory-tagging-extension.rst.
2156 Access Never to be used with Execute-only mappings.
2172 enforcing page-based protections, but without requiring modification
2175 For details, see Documentation/core-api/protection-keys.rst
2210 If you need the kernel to boot on SVE-capable hardware with broken
2229 bool "Support for NMI-like interrupts"
2232 Adds support for mimicking Non-Maskable Interrupts through the use of
2275 random u64 value in /chosen/kaslr-seed at kernel entry.
2302 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2310 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2343 Provide a set of default command-line options at build time by
2358 Uses the command-line options passed by the boot loader. If
2368 command-line options your boot loader passes to the kernel.
2390 by UEFI firmware (such as non-volatile variables, realtime
2415 continue to boot on existing non-UEFI platforms.