Kconfig - OpenGrok cross reference for /linux-6.12.1/arch/arm64/Kconfig

444 	  The affected design reports FEAT_HAFDBS as not implemented in
477 	  the kernel if an affected CPU is detected.
499 	  the kernel if an affected CPU is detected.
522 	  only patch the kernel if an affected CPU is detected.
544 	  the kernel if an affected CPU is detected.
555 	  Affected Cortex-A57 parts might deadlock when exclusive load/store
562 	  the kernel if an affected CPU is detected.
573 	  Affected Cortex-A57 parts might report a Stage 2 translation
582 	  the kernel if an affected CPU is detected.
594 	  Affected parts may corrupt the AES state if an interrupt is
610 	  When running a compat (AArch32) userspace on an affected Cortex-A53
619 	  the kernel if an affected CPU is detected.
643 	  Affected Cortex-A55 cores (all revisions) could cause incorrect
646 	  of hardware DBM locally on the affected cores. CPUs not affected by
659 	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
675 	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
701 	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
711 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
716 	  Under very rare circumstances, affected Cortex-A55 CPUs
721 	  Work around this by adding the affected CPUs to the list that needs
732 	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
749 	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
767 	  Affected Neoverse-N1 cores could execute a stale instruction when
782 	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
804 	  Affected Cortex-A510 might not respect the ordering rules for
806 	  is to not enable the feature on affected CPUs.
815 	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
832 	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
848 	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
866 	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
886 	  Affected cores may fail to flush the trace data on a TSB instruction, when
890 	  Workaround is to issue two TSB consecutively on affected cores.
901 	  Affected cores may fail to flush the trace data on a TSB instruction, when
905 	  Workaround is to issue two TSB consecutively on affected cores.
920 	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
938 	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
949 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
954 	  Under very rare circumstances, affected Cortex-A510 CPUs
959 	  Work around this by adding the affected CPUs to the list that needs
971 	  Affected Cortex-A510 core might fail to write into system registers after the
977 	  is stopped and before performing a system register write to one of the affected
989 	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1012 	  Affected Cortex-A510 core might cause trace data corruption, when being written
1017 	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
1031 	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1034 	  Work around this problem by returning 0 when reading the affected counter in
1036 	  is the same to firmware disabling affected counters.
1066 	  On an affected Cortex-A520 core, a speculatively executed unprivileged
1080 	  On an affected Cortex-A510 core, a speculatively executed unprivileged
1115 	  On affected cores "MSR SSBS, #0" instructions may not affect