arm/mm/proc-xscale.S

70 	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
76 	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
92 1:	mcr	p15, 0, \rd, c7, c2, 5		@ allocate D cache line
101 	bne	1b
117 	mrc	p15, 0, r1, c1, c0, 1
118 	bic	r1, r1, #1
119 	mcr	p15, 0, r1, c1, c0, 1
127 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
130 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
150 	mcr	p15, 0, r1, c10, c4, 1		@ unlock I-TLB
152 	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
157 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
160 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
181 	mov	r0, #1
182 	mcr	p14, 0, r0, c7, c0, 0		@ Go to IDLE
240 1:	tst	r2, #VM_EXEC
241 	mcrne	p15, 0, r0, c7, c5, 1		@ Invalidate I cache line
242 	mcr	p15, 0, r0, c7, c10, 1		@ Clean D cache line
243 	mcr	p15, 0, r0, c7, c6, 1		@ Invalidate D cache line
246 	blo	1b
267 	bic	r0, r0, #CACHELINESIZE - 1
268 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
271 	blo	1b
289 	bic	r0, r0, #CACHELINESIZE - 1
290 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
291 	mcr	p15, 0, r0, c7, c5, 1		@ Invalidate I cache entry
294 	blo	1b
312 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
313 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
316 	blo	1b
335 	tst	r0, #CACHELINESIZE - 1
336 	bic	r0, r0, #CACHELINESIZE - 1
337 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
338 	tst	r1, #CACHELINESIZE - 1
339 	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
340 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
343 	blo	1b
356 	bic	r0, r0, #CACHELINESIZE - 1
357 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
360 	blo	1b
373 	bic	r0, r0, #CACHELINESIZE - 1
374 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
375 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
378 	blo	1b
435 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
438 	bhi	1b
456 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
473 	.long	PTE_EXT_TEX(1) | PTE_BUFFERABLE			@ L_PTE_MT_DEV_SHARED
475 	.long	PTE_EXT_TEX(1) | PTE_CACHEABLE			@ L_PTE_MT_MINICACHE
476 	.long	PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE	@ L_PTE_MT_WRITEALLOC
515 	mrc	p14, 0, r4, c6, c0, 0	@ clock configuration, for turbo mode
517 	mrc	p15, 0, r6, c13, c0, 0	@ PID
518 	mrc	p15, 0, r7, c3, c0, 0	@ domain ID
519 	mrc	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
520 	mrc	p15, 0, r9, c1, c0, 0	@ control reg
531 	mcr	p14, 0, r4, c6, c0, 0	@ clock configuration, turbo mode.
533 	mcr	p15, 0, r6, c13, c0, 0	@ PID
534 	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
535 	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
536 	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
547 	mov	r0, #1 << 6			@ cp6 for IOP3xx and Bulverde
548 	orr	r0, r0, #1 << 13		@ Its undefined whether this
553 	mrc	p15, 0, r0, c1, c0, 0		@ get control register
572 	define_processor_functions xscale, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1