arm/mm/proc-xsc3.S

57 	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
69 1:	mcr	p15, 0, \rd, c7, c14, 2		@ clean/invalidate L1 D line
71 	bcc	1b
73 	bpl	1b
91 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
94 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
112 	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
115 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
118 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
139 	mov	r0, #1
140 	mcr	p14, 0, r0, c7, c0, 0		@ go to idle
199 1:	tst	r2, #VM_EXEC
200 	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate L1 I line
201 	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
204 	blo	1b
232 	bic	r0, r0, #CACHELINESIZE - 1
233 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
236 	blo	1b
255 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
258 	blo	1b
278 	tst	r0, #CACHELINESIZE - 1
279 	bic	r0, r0, #CACHELINESIZE - 1
280 	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
281 	tst	r1, #CACHELINESIZE - 1
282 	mcrne	p15, 0, r1, c7, c10, 1		@ clean L1 D line
283 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate L1 D line
286 	blo	1b
299 	bic	r0, r0, #CACHELINESIZE - 1
300 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
303 	blo	1b
316 	bic	r0, r0, #CACHELINESIZE - 1
317 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
320 	blo	1b
350 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
353 	bhi	1b
373 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
385 	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_BUFFERABLE
388 	.long	PTE_EXT_TEX(1) | PTE_BUFFERABLE			@ L_PTE_MT_DEV_SHARED
393 	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_DEV_WC
425 	mrc	p14, 0, r4, c6, c0, 0	@ clock configuration, for turbo mode
427 	mrc	p15, 0, r6, c13, c0, 0	@ PID
428 	mrc 	p15, 0, r7, c3, c0, 0	@ domain ID
429 	mrc	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
430 	mrc 	p15, 0, r9, c1, c0, 0	@ control reg
443 	mcr	p14, 0, r4, c6, c0, 0	@ clock configuration, turbo mode.
445 	mcr	p15, 0, r6, c13, c0, 0	@ PID
446 	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
448 	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
449 	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
464 	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
466 	mov	r0, #1 << 6			@ cp6 access for early sched_clock
469 	mrc	p15, 0, r0, c1, c0, 1		@ get auxiliary control reg
471 	orr	r0, r0, #(1 << 10)		@ enable L2 for LLR cache
472 	mcr	p15, 0, r0, c1, c0, 1		@ set auxiliary control reg
478 	mrc	p15, 1, r0, c0, c0, 1		@ get L2 present information
480 	orrne	r6, r6, #(1 << 26)		@ enable L2 if present
483 	mrc	p15, 0, r0, c1, c0, 0		@ get control register
498 	define_processor_functions xsc3, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1