arm/mm/proc-v7.S

35 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
38 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
58 	mrc	p15, 0, r2, c1, c0, 0		@ ctrl register
60  THUMB(	bic	r2, r2, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
61 	mcr	p15, 0, r2, c1, c0, 0		@ disable MMU
86 	ALT_UP_B(1f)
88 1:	dcache_line_size r2, r3
89 2:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
138 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
139 	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
142 	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
144 	mrrc	p15, 1, r5, r7, c2	@ TTB 1
146 	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
148 	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
150 	mrc	p15, 0, r8, c1, c0, 0	@ Control register
151 	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
152 	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
160 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
162 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
163 	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
167 	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
170 	mcrr	p15, 1, r5, r7, c2	@ TTB 1
174 	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
175 	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
177 	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
181 	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
183 	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
185 	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
186 	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
199 	mrc	p15, 0, r4, c15, c0, 1		@ Diagnostic register
200 	mrc	p15, 0, r5, c15, c0, 0		@ Power register
208 	mrc	p15, 0, r10, c15, c0, 1		@ Read Diagnostic register
210 	mcrne	p15, 0, r4, c15, c0, 1		@ No, so restore it
211 	mrc	p15, 0, r10, c15, c0, 0		@ Read Power register
213 	mcrne	p15, 0, r5, c15, c0, 0		@ No, so restore it
238 	mrc	p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
239 	mrc	p15, 1, r7, c15, c2, 0	@ save CP15 - Aux Func Modes Ctrl 0
240 	mrc	p15, 1, r8, c15, c1, 2	@ save CP15 - Aux Debug Modes Ctrl 2
241 	mrc	p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
250 	mcr	p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
251 	mcr	p15, 1, r7, c15, c2, 0	@ restore CP15 - Aux Func Modes Ctrl 0
252 	mcr	p15, 1, r8, c15, c1, 2	@ restore CP15 - Aux Debug Modes Ctrl 2
253 	mcr	p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
299 	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
300 	b	1f
308 1:
310 	orr	r10, r10, #(1 << 6)		@ Enable SMP/nAMP mode
311 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
315 	mcrne	p15, 0, r10, c1, c0, 1		@ No, update register
330 	mrceq	p15, 0, r0, c1, c0, 1		@ read aux control register
331 	orreq	r0, r0, #(1 << 6)		@ set IBE to 1
332 	mcreq	p15, 0, r0, c1, c0, 1		@ write aux control register
336 	mrceq	p15, 0, r0, c1, c0, 1		@ read aux control register
337 	orreq	r0, r0, #(1 << 5)		@ set L1NEON to 1
338 	orreq	r0, r0, #(1 << 9)		@ set PLDNOP to 1
339 	mcreq	p15, 0, r0, c1, c0, 1		@ write aux control register
343 	mrceq	p15, 1, r0, c9, c0, 2		@ read L2 cache aux ctrl register
344 	tsteq	r0, #1 << 22
345 	orreq	r0, r0, #(1 << 22)		@ set the Write Allocate disable bit
346 	mcreq	p15, 1, r0, c9, c0, 2		@ write the L2 cache aux ctrl register
353 	mrcle	p15, 0, r0, c15, c0, 1		@ read diagnostic register
354 	orrle	r0, r0, #1 << 4			@ set bit #4
355 	mcrle	p15, 0, r0, c15, c0, 1		@ write diagnostic register
361 	mrceq	p15, 0, r0, c15, c0, 1		@ read diagnostic register
362 	orreq	r0, r0, #1 << 12		@ set bit #12
363 	orreq	r0, r0, #1 << 22		@ set bit #22
364 	mcreq	p15, 0, r0, c15, c0, 1		@ write diagnostic register
368 	mrceq	p15, 0, r0, c15, c0, 1		@ read diagnostic register
369 	orreq	r0, r0, #1 << 6			@ set bit #6
370 	mcreq	p15, 0, r0, c15, c0, 1		@ write diagnostic register
374 	ALT_UP_B(1f)
375 	mrclt	p15, 0, r0, c15, c0, 1		@ read diagnostic register
376 	orrlt	r0, r0, #1 << 11		@ set bit #11
377 	mcrlt	p15, 0, r0, c15, c0, 1		@ write diagnostic register
378 1:
385 	mrcle	p15, 0, r0, c1, c0, 1		@ read aux control register
386 	orrle	r0, r0, #1 << 1			@ disable loop buffer
387 	mcrle	p15, 0, r0, c1, c0, 1		@ write aux control register
393 	mrc	p15, 0, r10, c15, c0, 1		@ read diagnostic register
394 	orr	r10, r10, #1 << 12		@ set bit #12
395 	mcr	p15, 0, r10, c15, c0, 1		@ write diagnostic register
398 	mrc	p15, 0, r10, c15, c0, 2		@ read internal feature reg
399 	orr	r10, r10, #1 << 1		@ set bit #1
400 	mcr	p15, 0, r10, c15, c0, 2		@ write internal feature reg
403 	mrc	p15, 0, r10, c15, c0, 1		@ read diagnostic register
404 	orr	r10, r10, #1 << 24		@ set bit #24
405 	mcr	p15, 0, r10, c15, c0, 1		@ write diagnostic register
408 	mrc	p15, 0, r10, c15, c0, 1		@ read diagnostic register
410 	mcr	p15, 0, r10, c15, c0, 1		@ write diagnostic register
417 	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
418 	orrle	r10, r10, #1 << 24		@ set bit #24
419 	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
423 	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
424 	orrle	r10, r10, #1 << 12		@ set bit #12
425 	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
428 	mrc	p15, 0, r10, c15, c0, 1		@ read diagnostic register
430 	mcr	p15, 0, r10, c15, c0, 1		@ write diagnostic register
437 /* Auxiliary Debug Modes Control 1 Register */
438 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
439 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
440 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
443 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
444 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
445 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
446 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
447 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
452 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
453 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
454 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
457 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
459 	/* Auxiliary Debug Modes Control 1 Register */
460 	mrc	p15, 1,	r0, c15, c1, 1
464 	mcr	p15, 1,	r0, c15, c1, 1
467 	mrc	p15, 1,	r0, c15, c1, 2
470 	mcr	p15, 1,	r0, c15, c1, 2
473 	mrc	p15, 1,	r0, c15, c2, 0
479 	mcr	p15, 1,	r0, c15, c2, 0
482 	mrc	p15, 1,	r0, c15, c1, 0
484 	mcr	p15, 1,	r0, c15, c1, 0
534 	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
538 	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
540 	teq	r0, #(1 << 12)			@ check if ThumbEE is present
541 	bne	1f
543 	mcr	p14, 6, r3, c1, c0, 0		@ Initialize TEEHBR to 0
544 	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
545 	orr	r0, r0, #1			@ set the 1st bit in order to
546 	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
547 1:
551  ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
553 	orr     r3, r3, #(1 << 10)              @ set SW bit in "clear"
554 	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
556    	mrc	p15, 0, r0, c1, c0, 0		@ read control register
559  THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
568 …define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bug…
583 …define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu…
604 …define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca…
619 …define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_…
637 …define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_c…
639 	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1