arm/mm/proc-v7-2level.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * arch/arm/mm/proc-v7-2level.S
27 .arch armv7-a
34  *	- pgd_phys - physical address of new TTB
37  *	- we are not using split page tables
40  *	even on Cortex-A8 revisions not affected by 430973.
45 	mmid	r1, r1				@ get mm->context.id
69  *	- ptep  - pointer to level 2 translation table entry
71  *	- pte   - PTE value to store
72  *	- ext	- value for extended PTE bits
115 	 *   TR = PRRR[2n+1:2n]		- memory type
116 	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
117 	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
133 	 *   DS0 = PRRR[16] = 0		- device shareable property
134 	 *   DS1 = PRRR[17] = 1		- device shareable property
135 	 *   NS0 = PRRR[18] = 0		- normal shareable property
136 	 *   NS1 = PRRR[19] = 1		- normal shareable property
137 	 *   NOS = PRRR[24+n] = 1	- not outer shareable
144 	 * - \ttb0 and \ttb1 updated with the corresponding flags.