arm/mm/proc-v6.S

23 #define TTB_C		(1 << 0)
24 #define TTB_S		(1 << 1)
25 #define TTB_IMP		(1 << 2)
27 #define TTB_RGN_WBWA	(1 << 3)
43 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
46 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
62 	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
64 	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
81 	mcr	p15, 0, r1, c7, c0, 4		@ wait for interrupt
86 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
89 	bhi	1b
111 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
113 	mrc	p15, 0, r2, c13, c0, 1		@ read current context ID
118 	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
148 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
150 	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
151 	mrc	p15, 0, r6, c2, c0, 1	@ Translation table base 1
153 	mrc	p15, 0, r7, c1, c0, 1	@ auxiliary control register
154 	mrc	p15, 0, r8, c1, c0, 2	@ co-processor access control
155 	mrc	p15, 0, r9, c1, c0, 0	@ control register
166 	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
168 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
170 	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
173 	mcr	p15, 0, r1, c2, c0, 0	@ Translation table base 0
174 	mcr	p15, 0, r6, c2, c0, 1	@ Translation table base 1
175 	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
177 	mcr	p15, 0, r7, c1, c0, 1	@ auxiliary control register
178 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
206 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)	@ Enable SMP/nAMP mode
209 	ALT_SMP(mcr	p15, 0, r0, c1, c0, 1)
219 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
224 	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
230  ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
231 	mrc	p15, 0, r0, c1, c0, 0		@ read control register
243 	mrc	p15, 0, r5, c0, c0, 0		@ get processor id
245 	mrceq	p15, 0, r5, c1, c0, 1		@ load aux control reg
246 	orreq	r5, r5, #(1 << 31)		@ set the undocumented bit 31
247 	mcreq	p15, 0, r5, c1, c0, 1		@ write aux control reg
248 	orreq	r0, r0, #(1 << 21)		@ low interrupt latency configuration
265 	define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1