arm/mm/proc-sa1100.S

42 	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
43 	mcr	p15, 0, r0, c9, c0, 5		@ Allow read-buffer operations from userland
55 	mcr	p15, 0, ip, c15, c2, 2		@ Disable clock switching
56 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
59 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
81 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
84 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
97  *   2 = switch to slow processor clock
111 	mcr	p15, 0, r0, c15, c2, 2		@ disable clock switching
113 	mcr	p15, 0, r0, c15, c8, 2		@ wait for interrupt
115 	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
152 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
153 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
182 	mrc	p15, 0, r4, c3, c0, 0		@ domain ID
183 	mrc	p15, 0, r5, c13, c0, 0		@ PID
184 	mrc	p15, 0, r6, c1, c0, 0		@ control reg
194 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
195 	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB
197 	mcr	p15, 0, r4, c3, c0, 0		@ domain ID
198 	mcr	p15, 0, r1, c2, c0, 0		@ translation table base addr
199 	mcr	p15, 0, r5, c13, c0, 0		@ PID
215 	mrc	p15, 0, r0, c1, c0		@ get control register v4