Lines Matching +full:1 +full:c0
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
141 1: tst r2, #VM_EXEC
142 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
143 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
146 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
149 blo 1b
184 bic r0, r0, #CACHE_DLINESIZE - 1
185 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
186 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
189 blo 1b
206 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
209 blo 1b
230 tst r0, #CACHE_DLINESIZE - 1
231 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
232 tst r1, #CACHE_DLINESIZE - 1
233 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
234 bic r0, r0, #CACHE_DLINESIZE - 1
235 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
238 blo 1b
253 bic r0, r0, #CACHE_DLINESIZE - 1
254 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
257 blo 1b
270 bic r0, r0, #CACHE_DLINESIZE - 1
271 1:
272 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
275 blo 1b
305 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
308 bhi 1b
327 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
342 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
355 mrc p15, 0, r6, c13, c0, 0 @ PID
356 mrc p15, 0, r7, c3, c0, 0 @ domain ID
357 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
358 mrc p15, 0, r9, c1, c0, 0 @ control reg
371 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
373 mcr p15, 0, r6, c13, c0, 0 @ PID
374 mcr p15, 0, r7, c3, c0, 0 @ domain ID
376 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
377 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
390 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
397 mrc p15, 0, r0, c1, c0 @ get control register